Reliability aspects of binary vector-matrix-multiplications using ReRAM devices

Abstract

Computation-In-Memory (CIM) using memristive devices is a promising approach to overcome the performance limitations of conventional computing architectures introduced by the von Neumann bottleneck which are also known as memory wall and power wall. It has been shown that accelerators based on memristive devices can deliver higher energy efficiencies and data throughputs when compared with conventional architectures. In the vast multitude of memristive devices, bipolar resistive switches (BRS) based on the valence change mechanism (VCM) are particularly interesting due to their low power operation, non-volatility, high integration density and their CMOS compatibility. While a wide range of possible applications is considered, many of them such as artificial neural networks heavily rely on Vector-Matrix-Multiplications (VMMs) as a mathematical operation. These VMMs are made up of large numbers of Multiplication and Accumulation (MAC) operations. The MAC operation can be realised using memristive devices in an analog fashion using Ohm’s law and Kirchhoff’s law. However, VCM devices exhibit a range of non-idealities, affecting the VMM performance, which in turn impacts the overall accuracy of the application. Those non-idealities can be classified into time-independent (programming variability) and timedependent (read disturb and read noise). Additionally, peripheral circuits such as Analog to Digital Converters (ADCs) can introduce errors during the digitalization. In this work, we experimentally and theoretically investigate the impact of deviceand circuit-level effects on the VMM in a VCM crossbars. Our analysis shows that the variability of the Low Resistive State (LRS) plays a key role and that reading in the RESET direction should be favored to reading in the SET direction.

Experimental Assessment of Multilevel RRAM-Based Vector-Matrix Multiplication Operations for In-Memory Computing

“…This is denoted by the more stable average LRS3 and HRS lines depicted in the figure, compared to those obtained from the intermediate levels. In our study, the later levels tend to suffer more from the device's nonidealities e.g., undesired resistance drifts and state relaxations, in agreement with [23] and [34]. Hence they are more prone to cause accuracy degradation in the output vector calculations.…”

“…However, to our best knowledge, the overall assessment of the RRAM MAC operation in a simulation environment is not yet fully performed and includes several simplifications due to the limits of the underlying hardware model [18], [19], [20], [21], [22]. Recently, Bengel et al [23] experimentally analyzed the impact of binary RRAM nonidealities in VMM operations highlighting the fact that the low resistive state (LRS) variability plays a major role compared to the high resistive state (HRS) variability when performing MAC operations. The results were supported by circuit-level simulations using the physics-based Jülich Aachen Resistive Switching Tools-valence change mechanism (JART VCM) model considering ZrO 2 /Ta-based devices [24].…”

Memristive Devices for Time Domain Compute-in-Memory

“…Under these assumptions and for the use case of an embedded memory, recent results have shown that read disturb is not a critical issue in advanced integrated technologies [36]. In [39],…”

“…However, for the sake of comparability, all voltages in this paper are given with respect to 0 V at the Ta/Pt top electrode. Further details on the device fabrication and the measurement setup can be found in [39]. Figure 4a shows implementations for binary TDCIM MAC cells in classical CMOS (a) compared to a memristor based solution (b) and the corresponding stick diagram (c).…”

Covalent Organic Frameworks for Neuromorphic Devices

“…74−76 Digital memory devices with bistable and switchable resistance states are typically configured with a two-terminal metal−insulator− metal structure, which have been demonstrated for neuromorphic computing. 4,77,78 Besides, analog memory devices with continuous resistance tunability, such as two-terminal memristive devices and three-terminal synaptic transistors, have also been proposed for mimicking artificial synapses in biological neuron networks. 79,80 Generally, resistive switching in inorganic materials can be explained by filamentary conduction, ion migration, electron transfer, etc.…”