Reliability-Aware Design of Spike-Event Neuromorphic Circuits

Abstract

Very Large Scale Integration (VLSI) based neuromorphic circuits also known as Silicon Neurons (SiNs) emulate the electrophysiological behavior of biological neurons. With the advancement in technology, neuromorphic systems also lead to various reliability issues and hence making their study important. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are the two major reliability issues present in VLSI circuits. In this work, we have investigated the combined effect of BTI and HCI on the two types of integrate-and-fire based SiNs namely (a) Axon-Hillock and (b) Simplified Leaky integrate-and-fire circuits using their key performance parameters. Novel reliability-aware AH and SLIF circuits are proposed to mitigate the reliability issues. Proposed reliability-aware designs show negligible deviation in performance parameters after aging. The time-zero process variability analysis is also carried out for proposed reliability-aware SiNs. The power consumption of existing and proposed reliability-aware neuron circuits is analyzed and compared.<br>

Reliability‐aware design of temporal neuromorphic encoder for image recognition

“…The third technique is to minimize shift in V TH of the transistor PM1 in the neuron module. A reduction in V TH shift can be achieved by employing a rel‐SLIF neuron in place of the conv‐SLIF neuron 40 . In the rel‐SLIF neuron circuit, a diode‐connected transistor PM4 is added to mitigate degradation in transistor PM1.…”

“…It is observed from figure that power dissipated by rel‐encoder is always lower than conv‐encoder for entire V IN range. It is reported that the rel‐SLIF neuron consumes less power than the conv‐SLIF neuron 40 . This is because the addition of the transistor PM4 lowers the voltage swing of the inverter output, which reduces the power consumption.…”