Reliability aware through silicon via planning for 3D stacked ICs

Shayan, Amirali; Hu, Xiang; He, Peng; Cheng, Chung‐Kuan; Yu, Wenjian; Popovich, Mikhail; Toms, T.; Chen, Xiaoming

doi:10.1109/date.2009.5090673

Cited by 17 publications

(7 citation statements)

References 6 publications

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“…The enhanced packing densities facilitated by 3D integrated circuit technology also have an unwanted side-effect, in the form of increasing the amount of current per unit footprint of the chip, as compared to a 2D design [3]. From the experimental results it is observed that a single TSV failure could increase the maximum voltage variation up to 70% in nano-scale ICs [4]. A 3D chip with n tiers can only have 1/n the number of power supply pins compared to its 2D counterpart which results in n fold increase in the resistive and inductive parasitic [5].…”

Section: Introductionmentioning

confidence: 89%

Modeling of peak-to-peak switching noise along a vertical chain of power distribution TSV pairs in a 3D stack of ICs interconnected through TSVs

et al. 2010

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On-chip power supply noise has become a bottleneck in 3D ICs as scaling of the supply network impedance has not been kept up with increasing device densities and operating currents with each technology node due to limited wire resources. In this paper we proposed an efficient and accurate model to estimate peak-topeak switching noise, caused by simultaneous switching of logic loads along a vertical chain of power distribution TSV pairs in a 3D stack of ICs. The proposed model is quite accurate with only 2-3% difference from Ansoft Nexxim4.1 equivalent model. The proposed model is 3-4 times faster than Nexxim4.1 as well as consumes two times less memory as compared to Nexxim4.1equivalent model. We analyzed peak-to-peak switching noise along a vertical chain of power distribution TSV pairs by varying physical dimensions of TSVs and value of decoupling capacitance. We also thoroughly investigated the peak-to-peak noise sensitivity to TSV effective inductance and decoupling capacitance.

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Section: Introductionmentioning

confidence: 89%

Modeling of peak-to-peak switching noise along a vertical chain of power distribution TSV pairs in a 3D stack of ICs interconnected through TSVs

et al. 2010

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“…It is a Reliability Computer Aided Design (RCAD) tool that is a capable of comparison of 2D and 3D circuit layouts. Similar to study of Alam et al, Shayan et al proposed a framework to analyze the reliability of 3D power distribution network under local through silicon via failures [17]. The 3D power distribution network is extracted and modeled in frequency domain considering skin effect.…”

Section: Related Workmentioning

confidence: 99%

Reliability-Aware Heterogeneous 3D Chip Multiprocessor Design

Akturk

Öztürk

2013

J Electron Test

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Ability to stack separate chips in a single package enables three-dimensional integrated circuits (3D ICs). Heterogeneous 3D ICs provide even better opportunities to reduce the power and increase the performance per unit area. An important issue in designing a heterogeneous 3D IC is reliability. To achieve this, one needs to select the data mapping and processor layout carefully. This paper addresses this problem using an integer linear programming (ILP) approach. Specifically, on a heterogeneous 3D CMP, it explores how applications can be mapped onto 3D ICs to maximize reliability. Preliminary experiments indicate that the proposed technique generates promising results in both reliability and performance.

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“…The silicon substrate is usually of low resistivity in digital ICs and this will lead to silicon substrate propagation during power delivery and as a result noise. To the best of the authors knowledge, none of the previous work on 3D power distribution [4], [1], [7], modeled and considered the impact of substrate coupling in power noise. One challenge that is introduced as a result of three dimensional stacking is parasitic interactions through the shared silicon substrate and among TSVs.…”

Section: D Pdn Model With Substrate Couplingmentioning

confidence: 99%

“…Shayan et al in [4], presented a reliability aware TSV planning considering thermo-mechanical stress. We adopt the methodology in [4] and proposed model for the substrate coupling and analyzed the impact of frequency dependent TSV and substrate parasitics on the voltage variation.…”

Section: Introductionmentioning

confidence: 99%

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3D stacked power distribution considering substrate coupling

Shayan

Zhang

et al. 2009

2009 IEEE International Conference on Computer Design

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Abstract-Reliable design of power distribution network for stacked integrated circuits introduces new challenges i.e., substrate coupling among through silicon vias (TSVs) and tiers grid in addition to reliability issues such as electromigration and thermo-mechanical stress, compared to conventional System on Chip (SoC). In this paper a comprehensive modeling of the TSV and stacked power grid with frequency dependent parasitic is proposed. The analytical model considers the impact of the substrate coupling between the TSVs and layers grid. A frequency domain based analysis flow is introduced to incorporate frequency dependent parasitics. The design of a reliable power distribution network is formulated as an optimization problem to minimize power noise under reliability and electro-migration constraints. Experimental results demonstrate the efficacy of the problem formulation and solution technique.

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Reliability aware through silicon via planning for 3D stacked ICs

Cited by 17 publications

References 6 publications

Modeling of peak-to-peak switching noise along a vertical chain of power distribution TSV pairs in a 3D stack of ICs interconnected through TSVs

Modeling of peak-to-peak switching noise along a vertical chain of power distribution TSV pairs in a 3D stack of ICs interconnected through TSVs

Reliability-Aware Heterogeneous 3D Chip Multiprocessor Design

3D stacked power distribution considering substrate coupling

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