Reliability challenges for the 10nm node and beyond

Stathis, James H.; Wang, M.; Southwick, Richard G.; Wu, Ernest Y.; Linder, B.; Liniger, E.; Bonilla, G.; Kothari, H.

doi:10.1109/iedm.2014.7047091

Cited by 30 publications

(25 citation statements)

References 2 publications

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“…In contrast of previous planar FETs, FinFET technology reveals its immunity to HCI effect. A latter research can be further expanded to different fin width and gate underlap area so as to optimize the junction profile to achieve better device reliability/performance in sub-14nm gate length device suites [9]. Experimental results in device group without LDD implantation show improved electrostatic characteristic, reduced device Vtsat mismatch, and retained device reliability of HCI as compared to device group with LDD.…”

Section: Discussionmentioning

confidence: 98%

Electrical Characteristics of LDD and LDD-Free FinFET Devices of Dimension Compatible With 14 nm Technology Node

Hassan

Zhao

et al. 2020

IEEE J. Electron Devices Soc.

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FinFET devices with and without LDD implantation has been studied for dimensions compatible with leading 14nm technology node. Devices without LDD have better electrostatic characteristics with SS = 65mV/dec and DIBL = 33mV. The nFET transistors with no LDD have device Vtsat mismatch reduction by 20%, together with retained device reliability of HCI as compared to devices with LDD. A full range of device Vtsat flavors is enabled in this experiment, presenting excellent device performances at different operating voltages of 0.55V, 0.8V and 1.2V. All results indicates that devices with no LDD and one less mask in FinFET architecture achieve lower cost, compelling performance and area scaling compared to devices with LDD, for high performance and low power applications.

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Section: Discussionmentioning

confidence: 98%

Electrical Characteristics of LDD and LDD-Free FinFET Devices of Dimension Compatible With 14 nm Technology Node

Hassan

Zhao

et al. 2020

IEEE J. Electron Devices Soc.

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“…The dimension of effective devices has shrunk to a sub-22 nanometer scale, and due to this, we are facing even more serious characteristic variability problems [1,2,3,4,5,6,7]. High-κ/metal gate (HKMG) technology has been recognized as a solution to solve intrinsic fluctuation, but the crystal orientation of nanosized metal grain is uncontrollable during the growth step under high temperatures [8,9].…”

Section: Introductionmentioning

confidence: 99%

Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits

Chen

Chuang

et al. 2019

Materials

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In this study, we investigate direct current (DC)/alternating current (AC) characteristic variability induced by work function fluctuation (WKF) with respect to different nanosized metal grains and the variation of aspect ratios (ARs) of channel cross-sections on a 10 nm gate gate-all-around (GAA) nanowire (NW) metal–oxide–semiconductor field-effect transistor (MOSFET) device. The associated timing and power fluctuations of the GAA NW complementary metal–oxide–semiconductor (CMOS) circuits are further estimated and analyzed simultaneously. The experimentally validated device and circuit simulation running on a parallel computing system are intensively performed while considering the effects of WKF and various ARs to access the device’s nominal and fluctuated characteristics. To provide the best accuracy of simulation, we herein calibrate the simulation results and experimental data by adjusting the fitting parameters of the mobility model. Transfer characteristics, dynamic timing, and power consumption of the tested circuit are calculated using a mixed device–circuit simulation technique. The timing fluctuation mainly follows the trend of the variation of threshold voltage. The fluctuation terms of power consumption comprising static, short-circuit, and dynamic powers are governed by the trend that the larger the grain size, the larger the fluctuation.

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“…In advanced nanoscale CMOS technology, reliability is one of the main concerns for circuit design and modelling [1][2][3][4][5][6]. Both Hot Carrier Aging (HCA) and Positive Bias Temperature Instability (PBTI) become severer with shorter channel length and use of high-k gate dielectrics.…”

Section: Introductionmentioning

confidence: 99%

Interaction between hot carrier aging and PBTI degradation in nMOSFETs: Characterization, modelling and lifetime prediction

Duan

Zhang

et al. 2017

2017 IEEE International Reliability Physics Symposium (IRPS)

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Modelling of the interaction between Hot Carrier Aging (HCA) and Positive Bias Temperature Instability (PBTI) has been considered as one of the main challenges in nanoscale CMOS circuit design. Previous works were mainly based on separate HCA and PBTI instead of Interacted HCA-PBTI Degradation (IHPD). The key advance of this work is to develop a methodology that enables accurate modelling of IHPD through understanding the charging/discharging and generation kinetics of different types of defects during the interaction between HCA and PBTI. It is found that degradation during alternating HCA and PBTI stress cannot be modelled by independent HCI/PBTI. Different stress sequence, i.e. HCA-PBTI-HCA and PBTI-HCA-PBTI, lead to completely different degradation kinetics. Based on the Cyclic Anti-neutralization Model (CAM), for the first time, IHPD has been accurately modelled for both short and long channel devices. Complex degradation mechanisms and kinetics can be well explained by our model. Our results show that device lifetime can be underestimated by one decade without considering interaction.

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Reliability challenges for the 10nm node and beyond

Cited by 30 publications

References 2 publications

Electrical Characteristics of LDD and LDD-Free FinFET Devices of Dimension Compatible With 14 nm Technology Node

Electrical Characteristics of LDD and LDD-Free FinFET Devices of Dimension Compatible With 14 nm Technology Node

Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits

Interaction between hot carrier aging and PBTI degradation in nMOSFETs: Characterization, modelling and lifetime prediction

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