Reliability driven guideline for BEOL Optimization: Protecting MOS stacks from hydrogen-related impurity penetration

Liu, Ziyuan; Hayashi, F.; Fujieda, Shinji; Wilde, Markus; Fukutani, Katsuyuki

doi:10.1109/icicdt.2012.6232838

Cited by 1 publication

(1 citation statement)

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“…As an essential procedure for the fabrication of 3D NAND, N2-annealing is expected to introduce a thin layer of Si2N2O on the surface of Si3N4. [22,23] This issue is also expected to be more serious with size scaling. As a unique compound in the SiO2-Si3N4 quasi-binary system, the intrinsic Si2N2O has long been studied intensively.…”

Section: Introductionmentioning

confidence: 99%

Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory

Wang

et al. 2021

IEEE Access

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In charge-trap (CT) three-dimensional (3D) NAND flash memory, the transition layer between Si3N4 CT layer and SiO2 tunneling layer is inevitable, and the defects in the transition layer are expected to cause both lateral and vertical charge loss. Here, by first-principles calculations, we present a detailed study on the defects in the transition layer Si2N2O to comprehend their impacts on charge loss in CT 3D NAND flash memory. It is shown that shallow-trap centers, such as intrinsic nitrogen vacancy (VN) and interstitial Ti (Tii), can couple with the conduction band of Si2N2O to lead to lateral charge loss. On the other hand, the N substituting Si atom (NSi) and Ti substituting Si atom (TiSi) defects in the transition layer can couple through resonance with the trap centers in Si3N4, leading to vertical charge loss from the CT layer to the transition layer. Our results strongly suggest that appropriate treatment of the transition layer and hydrogen passivation are both important for avoiding charge loss in CT 3D NAND flash memory.

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Section: Introductionmentioning

confidence: 99%