Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches

Elsharkasy, Wael M.; Khajeh, Amin; Eltawil, Ahmed M.; Kurdahi, Fadi

doi:10.1109/tcsi.2017.2680433

Cited by 9 publications

(2 citation statements)

References 24 publications

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“…However, they occupy a substantial chip area consuming high power. Researchers proposed many low-power flip-flops, however, not suitable for resonant operations [6,11,32,44,45,49]. In this research, we propose several conventional register-based pulsed FFs suitable for series resonance and reduce the overall power consumption in the clock network.…”

Section: Hfkqrorj\ 1rgh Qp 5hodwlyh 3rzhu Shu Qpamentioning

confidence: 99%

Design Automation of Series Resonance Clocking in 14-nm FinFETs

Challagundla,

Bezzam,

Islam

2023

Circuits Syst Signal Process

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Power-performance constraints have been the key driving force that motivated the microprocessor industry to bring unique design techniques in the past two decades. The rising demand for high-performance microprocessors increases the circuit complexity and data transfer rate, resulting in higher power consumption. This work proposes a set of energy recycling resonant pulsed flip-flops to reuse some of the dissipated energy using series inductor-capacitor (LC) resonance. Moreover, this work also presents wideband clocking architectures that use series LC resonance and an inductor tuning technique. By employing pulsed resonance, the switching power dissipated is recycled back. The inductor tuning technique aids in reducing the skew, increasing the robustness of the clock networks. This new resonant clocking architecture saves over 43% power and 90% reduced skew in clock tree networks and saves 44% power and 90% reduced skew in clock mesh networks, clocking a range of 1-5 GHz frequency, compared to conventional primary-secondary flip-flop-based clock networks. Implementation of resonant clock architectures on standard clock network benchmarks depicts 66% power Dhandeep Challagundla

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Section: Hfkqrorj\ 1rgh Qp 5hodwlyh 3rzhu Shu Qpamentioning

confidence: 99%

Design Automation of Series Resonance Clocking in 14-nm FinFETs

Challagundla,

Bezzam,

Islam

2023

Circuits Syst Signal Process

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“…The total power consumption is the combination of dynamic, static and short circuit powers and is given in (1) [25][26].…”

Section: Proposed Designmentioning

confidence: 99%

Effect of clock gating in conditional pulse enhancement flip-flop for low power applications

John¹,

S.²,

Kumar³

2019

IJEEI

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Flip-Flops (FFs) play a fundamental role in digital designs. A clock system consumes above 25% of total system power. The use of pulse-triggered flipflops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. This flipflop architecture is embedded with two key features. Firstly, the enhancement in width and height of triggering pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90-nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P-FFs. Its maximum power saving against conventional designs is up to 30.65%.

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Design of a Highly Reliable and Reconfigurable Pulsed Latch Circuits

Keerthi

Ragini

2019

Lecture Notes in Networks and Systems

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Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches

Cited by 9 publications

References 24 publications

Design Automation of Series Resonance Clocking in 14-nm FinFETs

Design Automation of Series Resonance Clocking in 14-nm FinFETs

Effect of clock gating in conditional pulse enhancement flip-flop for low power applications

Design of a Highly Reliable and Reconfigurable Pulsed Latch Circuits

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