Reliability evaluation on low k wafer level packages

Yadav, Praveen; Kalchuri, Shantanu; Keser, Beth; Zang, Ricky; Schwarz, M. Philip; Stone, Bill

doi:10.1109/ectc.2011.5898494

Cited by 13 publications

(2 citation statements)

References 10 publications

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“…The electromigration performance of the baseline WLP package construction with a 5um polyimide passivation, 4um Cu RDL metal, a second 5um polyimide passivation, 8.6um thick Cu UBM and a SAC405 solder ball was reported previously [6]. The board level reliability of a similar construction has also been reported previously [7].…”

Section: Introductionmentioning

confidence: 86%

A study of wafer level package board level reliability

Keser

Hau-Riege

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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Board level reliability studies have been performed on wafer level packages (WLP) with various solder ball alloys, underbump metallurgy compositions, and redistribution (RDL) metal thicknesses. All of the WLPs studied pass drop shock with the thicker RDL having the best performance. In contrast to drop shock, , thicker RDL did not significantly improve thermal cycle on board reliability. A WLP with no underbump metallurgy (UBM) passed drop shock, but the temperature cycle performance was marginal. A WLP with Ni-doped alloy and NiCu UBM passed drop shock; however, this Ni-rich joint failed temperature cycle.

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Section: Introductionmentioning

confidence: 86%

A study of wafer level package board level reliability

Keser

Hau-Riege

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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“…Over the past years, due to the increasing demand of packaging types with lower costs, smaller footprints, and improved functionality, WLP technologies have gained widespread adoptions and rapidly penetrated into many consumer electronic markets, such as mobile handsets, cameras, and laptop/ tablet computers [1][2].…”

Section: Introductionmentioning

confidence: 99%

Wafer level package wafer probing shift error-proof quality control

Jin

Qiao

et al. 2015

2015 IEEE International Conference on Industrial Engineering and Engineering Management (IEEM)

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Wafer level package (WLP) is one of the fastest growing segments in the semiconductor packaging industries. Low costs, small sizes, and the ease of logistics make WLP a main-stream packaging solution for a single chip. However, different from conventional packages, WLP has no final test (FT) and only relies on wafer level probing for functional test, which may induce the trouble that once wafer probing map shifts, the functionally failed dice will be shipped as good ones and result in huge economic compensations. In such situation, based on manufacturing experiences and actual experimental data, this paper provided preventive guidelines and detecting solutions to eliminate the impact from wafer probing shifts.

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Fan-In Wafer/Panel-Level Chip-Scale Packages

Lau

2021

Semiconductor Advanced Packaging

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Reliability evaluation on low k wafer level packages

Cited by 13 publications

References 10 publications

A study of wafer level package board level reliability

A study of wafer level package board level reliability

Wafer level package wafer probing shift error-proof quality control

Fan-In Wafer/Panel-Level Chip-Scale Packages

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