Reliability for Recessed Channel Structure n-MOSFET

Seo, Jihoon; Lee, K.J.; Kim, Y.S.; Lee, S.Y.; Hwang, Soon Jung; Yoon, Cha Keun

doi:10.1016/j.microrel.2005.07.013

Cited by 28 publications

(11 citation statements)

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“…The fabrication of TRC structure is feasible by implementing the fabrication process used by Xiao-Hua et al [16] and Seo et al [17] for grooved gate MOSFET. Further, for GME architecture, many fabrication schemes has been suggested such as inter diffusion process [18,19] and tilt angle evaporation (TAE) [20,21] which makes the fabrication possible even in sub-100 nm regime.…”

Section: Fabrication Feasibility Of Gme-trc Mosfetmentioning

confidence: 99%

Linearity-Distortion Analysis of GME-TRC MOSFET for High Performance and Wireless Applications

Malik¹,

Gupta²,

Chaujar³

et al. 2011

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this present paper, a comprehensive drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: g m1 , g m2 , g m3 , and figure-of-merit (FOM) metrics; V IP2 , V IP3 , IIP3 and 1-dB compression point, has been obtained. It is shown that, the incorporation of multi-layered architecture on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET leads to improved linearity performance in comparison to its conventional counterparts trapezoidal recessed channel (TRC) and rectangular recessed channel (RRC) MOSFETs, proving its efficiency for low-noise applications and future ULSI production. The impact of various structural parameters such as variation of work function, substrate doping and source/drain junction depth (X j ) or negative junction depth (NJD) have been examined for GME-TRC MOSFET and compared its effectiveness with MLGME-TRC MOSFET. The results obtained from proposed model are verified with simulated and experimental results. A good agreement between the results is obtained, thus validating the model.

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Section: Fabrication Feasibility Of Gme-trc Mosfetmentioning

confidence: 99%

Linearity-Distortion Analysis of GME-TRC MOSFET for High Performance and Wireless Applications

Malik¹,

Gupta²,

Chaujar³

et al. 2011

JSTS:Journal of Semiconductor Technology and Science

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“…Recessed channel is the most efficient channel engineering technology which introduces the concept of negative junction depth (NJD) as a structural parameter for optimization of device performance . By incorporating this technology in SOI‐MOSFET, ie, introducing a groove between source and drain regions, penetration of drain side depletion region is less towards the source side thus minimizes the hot‐carrier immunity and punch through effects .…”

Section: Introductionmentioning

confidence: 99%

“…[12][13][14][15] By incorporating this technology in SOI-MOSFET, ie, introducing a groove between source and drain regions, penetration of drain side depletion region is less towards the source side thus minimizes the hot-carrier immunity and punch through effects. [16][17][18][19][20] Different techniques like plasma etching, shallow trench isolation, and reactive ion etching have been adopted for fabrication of grooved gate MOSFETs. 12,16 Device scaling reduces the gate control on threshold voltage.…”

mentioning

confidence: 99%

“…[16][17][18][19][20] Different techniques like plasma etching, shallow trench isolation, and reactive ion etching have been adopted for fabrication of grooved gate MOSFETs. 12,16 Device scaling reduces the gate control on threshold voltage. So, a new structure is proposed by implementing the gate engineering called dual material gate MOSFET, where source side gate material has higher workfunction than the drain side gate material.…”

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confidence: 99%

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Variation of source gate workfunction on the performance of dual material gate rectangular recessed channel SOI‐MOSFET

Mishra

Bhanja

Mishra

2018

Int J Numerical Modelling

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This paper attempts to propose a new device as workfunction modulated dual metal rectangular recessed channel silicon on insulator (WMDMRRC-SOI) MOSFET. This model takes the advantage of recessed channel to reduce the hot-carrier effect and a linear variation of workfunction at source side metal gate to achieve improved threshold voltage and electron transportation efficiency. The characteristics of WMDMRRC-SOI MOSFET are analyzed in terms of electron behaviour like mobility, temperature, and velocity in the channel region. The impact of negative junction depth on threshold voltage and short-channel effects like drain induced barrier lowering, subthreshold slope are analyzed to optimize the characteristics of the proposed architecture.Performance parameters of WMDMRRC-SOI MOSFET are compared with the results of DMRRC-SOI MOSFET and conventional RRC-SOI MOSFET.The comparison interprets that with higher intrinsic gain and lower distortion, the proposed architecture gives better analog performance and enhanced short channel parameters. The results obtained are validated through Sentaurus TCAD device simulator. KEYWORDSnegative junction depth (NJD), recessed channel (RC), short-channel effects, silicon-on-insulator (SOI) | INTRODUCTIONScaling of MOS dimensions is essential in order to realize a high-speed and higher-packing density MOS integrated circuit, which results in high power consumption. Attempts to reduce power consumption lead to the degradation of MOSFET carrier transport efficiency. With aggressive technology scaling, the improvement in device reliability has been the prime focus in scaled MOSFET. Thus, performance enhancement can be achieved by overcoming the undesirable short-channel effects. [1][2][3] These barriers can be overcome by silicon-on-insulator (SOI) technology, which is implemented by assimilating an oxide layer on silicon body giving a perfect isolation to avoid latch up in conventional MOS structure. MOSFET along with SOI technology is popular for high temperature applications, as it provides lower leakage current at source/drain junction. Due to its better radiation tolerance, it is also useful for space applications. Above all, the steeper subthreshold characteristics make this device suitable for faster switching circuit applications. Although SOI technology is widely used, still some problems like gate transport inefficiency persists. 4-11

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“…Various fabrication techniques of grooved gate/RC MOSFETs [7,18,19] and multilayered gate dielectric architecture [20,21] have been reported in the literature. Further, several integration schemes for workfunction engineered gate electrodes have already been suggested in past such as tilt angle evaporation metal gate deposition [14], metal interdiffusion process [22,23], fully silicided metal gate [24], chemical mechanical polishing [25] and II method poly-Si gate doping control [26].…”

Section: Introductionmentioning

confidence: 99%

Investigation of multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) sub‐50 nm MOSFET: A novel design

Chaujar

Kaur

Saxena

et al. 2008

Int J Numerical Modelling

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SUMMARYIn this paper, a two-dimensional (2D) analytical sub-threshold model for a novel sub-50 nm multilayered-gate electrode workfunction engineered recessed channel (MLGEWE-RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO 2 -based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain-induced barrier lowering, sub-threshold drain current and sub-threshold swing. Results reveal that MLGEWE-RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high-speed integration circuits and analog design.

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Reliability for Recessed Channel Structure n-MOSFET

Cited by 28 publications

References 1 publication

Linearity-Distortion Analysis of GME-TRC MOSFET for High Performance and Wireless Applications

Linearity-Distortion Analysis of GME-TRC MOSFET for High Performance and Wireless Applications

Variation of source gate workfunction on the performance of dual material gate rectangular recessed channel SOI‐MOSFET

Investigation of multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) sub‐50 nm MOSFET: A novel design

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