Reliability Influences from Electrical Overstress on LSI Devices

Hart, Arthur R.; Teng, T.C.; McKenna, Arn

doi:10.1109/irps.1980.362938

Cited by 6 publications

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confidence: 99%

“…His findings showed that device breakdown may occur at voltages as low as 100V. Two years later, Hart et al published another study relating to the electrical overstress damage to large scale integrated circuits (LSI) with reference to ESD [2].With the fast growing interest in ESD, a number of papers started to appear dealing with the associated failure modes. Unger, in particular, pointed out that ESD could result in short or open circuits in MOS structures [3].…”

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Electrostatic discharge

Meniconi

1997

International Journal of Quality &Amp; Reliability Management

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IntroductionThe invention of the metal-oxide-semiconductor(MOS) transistor introduced a new failure phenomenon to the semiconductor industry. Although the effects of electrostatic discharge (ESD) have been noted previously, their presence was strongly felt in this new technology. In 1978, Schreier pointed out that MOS Field Effect Transistors (MOSFETs) are most susceptible to ESD damage [1]. His findings showed that device breakdown may occur at voltages as low as 100V. Two years later, Hart et al. published another study relating to the electrical overstress damage to large scale integrated circuits (LSI) with reference to ESD [2].With the fast growing interest in ESD, a number of papers started to appear dealing with the associated failure modes. Unger, in particular, pointed out that ESD could result in short or open circuits in MOS structures [3]. Early models for testing MOS devices with respect to ESD have been introduced by Goel in 1981[4], Hart et al. [5], and in 1983 MIL-STD-883C appeared, standardizing test procedures for ESD events through Method 3015.7. However, even before this standard was published, some research pointed out that the models used may not necessarily be representative of a working environment [6]. Since then, MIL-STD-883D (1991) has appeared with a revised version of Method 3015.7, Electrostatic Discharge Susceptibility Classification.Emphasis was put on trying to determine the static charge build-up which might occur for various materials and the associated human interaction. Some typical figures were published by Moss in 1982 [7]. The same year, the EOS (electric overstresses)/ESD Association formed. It was at the time estimated that over $5 billion worth of damage may be attributed to ESD [8]. Turner[9] also pointed out that static voltages of over 2kV may easily be generated. As a result, problems at the wafer level may occur during the actual manufacture of integrated circuits.

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Section: Introductionmentioning

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Electrostatic discharge

Meniconi

1997

International Journal of Quality &Amp; Reliability Management

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“…Typically, ESD pulses damage gate oxides or melting of small I amounts of the device, creating minute explosions, voids, cratering, and subsequent short circuit or open circuit on the device surface. Higher temperature 5 result in a significant reduction in the electrostatic discharge resistance of the component [Kuo 1983, Hart 1980. Typically, ESD failures result in fracture of the gate oxide in MOS I devices,since voltage is in excess of the breakdown voltage (in bipolar devices,…”

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The Influence of Temperature on Microelectronic Device Failure Mechanisms. Phase 2

Pecht¹

1993

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Electrostatic pulse breakdown in nmos devices

Amerasekera

Campbell

1986

Quality & Reliability Eng

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The electrostatic discharge (ESD) sensitivity of small dimension n-channel metal oxide semiconductor (NMOS) field effect transistors (FETs) has been investigated. NMOS FETs of varying dimensions and a constant gate oxide thickness of 40OA were each subjected to a single ESD voltage pulse of between 50 and 250V at temperatures between 25 and 200°C. Over 4000 devices were used, all resident on a single 3 inch silicon wafer. The object of the experiment was to determine the dependence of device ESD sensitivity on temperature, voltage and device dimensions as well as to investigate the mechanisms that cause oxide breakdown as a result of ESD damage.No temperature dependence of device ESD sensitivity was observed within the range of the experiment. A significant voltage dependence was observed, with degradation accounting for over 80 per cent of devices at 250V. A cumulative ESD effect was observed, whereby the degradation of device performance was found to increase with the number of applied pulses. Analysis of the breakdown characteristics revealed that the cause of damage was oxide breakdown. Application of the ESD pulse appears to lead to oxide breakdown through impact ionization within the oxide, the very short duration of the pulse not being favourable to processes involving electron trapping unless these traps are already present in the oxide.

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Reliability Influences from Electrical Overstress on LSI Devices

Cited by 6 publications

References 0 publications

Electrostatic discharge

Electrostatic discharge

The Influence of Temperature on Microelectronic Device Failure Mechanisms. Phase 2

Electrostatic pulse breakdown in nmos devices

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