Reliability issues in MuGFET nanodevices

Groeseneken, G.; Crupi, Felice; Shickova, A.; Thijs, S.; Linten, Dimitri; Kaczer, B.; Collaert, N.; Jurczak, M.

doi:10.1109/relphy.2008.4558863

Cited by 29 publications

(10 citation statements)

References 28 publications

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“…The author show that the behavior of time-dependent dielectric breakdown (TDDB) is not changed on the triple-gate architecture under different gate voltages and temperatures. This is also corroborated in the work conducted by Groeseneken et al [21], which further demonstrate that FinFET devices tend to suffer from more severe NBTI degradation. In [39], Wang et al analyze the soft-error resilience of FinFET devices and conclude that FinFET circuit is more reliable than bulk CMOS circuit in terms of soft-error immunity.…”

Section: B Performance Overheadsupporting

confidence: 78%

“…As can be seen, compared to a traditional planar transistor, the FinFET structure is designed with additional fin sidewall surface with higher availability of Si-H bonds [21] [41], implying larger chances of forming interface trap and consequently expediting the device degradation.…”

Section: A Nbti Degradation Mechanismmentioning

confidence: 99%

“…One of the most daunting conundrums is the increasing aging rate caused by negative bias temperature instability (NBTI). Recent experimental studies demonstrate that FinFET transistors are more vulnerable to NBTI, leading to a shorter lifetime than a planar device [21] [41]. The NBTI aging rate is evaluated by the increase of delay on the critical path after a certain amount of service time.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Mitigating NBTI Degradation on FinFET GPUs through Exploiting Device Heterogeneity

Zhang

Chen

Peng

et al. 2014

2014 IEEE Computer Society Annual Symposium on VLSI

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Recent experimental studies reveal that FinFET devices commercialized in recent years tend to suffer from more severe NBTI degradation compared to planar transistors, necessitating effective techniques on processors built with FinFET for endurable operations. We propose to address this problem by exploiting the device heterogeneity and leveraging the slower NBTI aging rate manifested on the planar devices. We focus on modern graphics processing units in this study due to their wide usage in the current community. We validate the effectiveness of the technique by applying it to the warp scheduler and demonstrate NBTI degradation is considerably alleviated with slight performance overhead.

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Section: B Performance Overheadsupporting

confidence: 78%

Section: A Nbti Degradation Mechanismmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Mitigating NBTI Degradation on FinFET GPUs through Exploiting Device Heterogeneity

Zhang

Chen

Peng

et al. 2014

2014 IEEE Computer Society Annual Symposium on VLSI

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“…Despite all the advantages of FinFET technology, its novel geometrical structure raises new reliability concerns. Multi-gate devices with standard orientation are more susceptible to BTI than planar devices due to the higher availability of Si-H bonds at the (110) oriented fin sidewalls [12]. (110) Oriented sidewall improves mobility and lead to better performance but it can also affect the interface quality [13].…”

Section: Bti and 14 Nm Finfet Characteristics 21 Finfet Bti Reliabilitymentioning

confidence: 99%

TCAD analysis and modeling for NBTI mechanism in FinFET transistors

Herrera-Moreno

Garcia-Gervacio

Villacorta-Minaya

et al. 2018

IEICE Electron. Express

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Aging is an important concern in long term reliability of semiconductor devices. In this regard, Bias Temperature Instability (BTI) is considered the major aging mechanism in nanometer regime, particularly in FinFET devices. Therefore, a well understanding of BTI mechanism in FinFET technology is of high interest. In this paper, a three-dimensional TCAD analysis about the impact of negative BTI (NBTI) FinFET technology is presented. In addition, a new NBTI degradation model is proposed for FinFET devices that can be incorporated in Spice which allow to consider aging of a circuit in a design phase. The three-dimensional TCAD analysis is performed using Synopsys Sentaurus tool. Results from the proposed model agree with Sentaurus degradation results.where B is the scaling factor and β is the dispersive shape factor. According to [21] and [19], ¼ 0:25 and B ¼ 1:5. The resulting graphic is shown in Fig. 4.

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“…Recent experimental investigations indicate that Multi-Gate FET devices with standard orientation exhibit worse NBTI than planar devices due to the higher availability of Si-H bonds at the (110) oriented fin sidewalls [2]. Depending on the electrical connection, i.e., shorted or isolated, between its gates, FinFET can operate at either on Shorted-Gate (SG) mode or Independent-Gate (IG) mode.…”

Section: Introductionmentioning

confidence: 99%

Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices

Wang

Cotöfană

Fang

2012

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures

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Abstract-As planar MOSFETs is approaching its physical scaling limits, FinFET becomes one of the most promising alternative structure to keep on the industry scaling-down trend for future technology generations of 22 nm and beyond. In this paper, we propose a statistical model of Negative Bias Temperature Instability (NBTI) tailored for FinFET SRAM Arrays. The model build upon an extension of the reaction-diffusion theory such that it can cover the natural variations encountered in nanoscale MOSFET circuits. Dynamic NBTI stress on SRAM cells is modeled by using stochastic input signals. A mitigation technology for minimizing the NBTI aging is also demonstrated by taking advantage of the independent-gate FinFET device structure using threshold voltage adjustment. We evaluated the impact of our proposal on the RAM stability by means of SPICE simulations with the BSIM-IMG Model for 22nm FinFET devices. Our simulations conducted at an accelerated temperature 125• C for 10 8 seconds (∼3 years) indicate that a V th compensation of 0.2V can almost preserve the WRITE and HOLD stability of the fresh device even after 3 years, while for the READ stability the compensation mechanism is less effective. However, the READ Static Noise Margin (SNM) experiences an insignificant decrease over the 3 years time span in the presence of a V th compensation, while without compensation it decreases by a x4 factor. Thus we can conclude that the proposed technique can improve the stability of SRAM array during its operational life, hence improve the performance and reliability of the system.

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Reliability issues in MuGFET nanodevices

Cited by 29 publications

References 28 publications

Mitigating NBTI Degradation on FinFET GPUs through Exploiting Device Heterogeneity

Mitigating NBTI Degradation on FinFET GPUs through Exploiting Device Heterogeneity

TCAD analysis and modeling for NBTI mechanism in FinFET transistors

Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices

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