Reliability Modeling and Analysis of Fault-Tolerant Memories

Cox, Glenn W.; Carroll, B. D.

doi:10.1109/tr.1978.5220238

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Fault-tolerant Computing As It Applies To Vlsi1

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1980

1992

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Cited by 15 publications

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“…Mathur and de Sousa [40] present a technique which uses reconfigurable NMR. Papers by Cox and Carroll [41] and Hartwell et al [42] describe approaches which involve swapping memory bit planes. Hsiao and Bossen [43 ] use orthogonal latin squares in reconfiguring the address lines of individual bit planes.…”

Section: Fault-tolerant Computing As It Applies To Vlsimentioning

confidence: 99%

Acceptable Testing of VLSI Components Which Contain Error Correctors

Cliff

1980

IEEE J. Solid-State Circuits

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If a VLSI chip is partitioned into functional units (NJ's) and redundant FU'S are added, error correcting codes maybe employed to increase the yield and/or reliability of the chip. Acceptable testing is defined to be testing the chip with the error corrector functioning, thns obtaining the maximum increase in yield afforded by the error correction. The acceptable testing theorem shows that the use of coding and error correction in conjunction with acceptable testing can significantly increase the yield of VLSI chips without seriously compromising their reliability.

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Section: Fault-tolerant Computing As It Applies To Vlsimentioning

confidence: 99%