Reliability of 3D NAND Flash Memories

Grossi, Alessandro; Zambelli, Cristian; Olivo, P.

doi:10.1007/978-94-017-7512-0_2

Cited by 13 publications

(13 citation statements)

References 28 publications

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“…Other recent works [23,31,78,80,92] report several differences of 3D NAND flash memory from planar NAND flash memory. These differences include (1) smaller program variation at high P/E cycle counts [80], (2) smaller program interference [80], (3) layer-to-layer process variation [92], (4) early retention loss [23,31,78], and (5) retention interference [23]. While prior works have reported on the existence of these errors, none of them provide a comprehensive characterization of all of the different errors using the same chips.…”

Section: Related Workmentioning

confidence: 99%

“…Two other recent works use a methodology similar to ours to characterize 3D NAND devices based on different 3D NAND flash memory cell technologies (i.e., 3D floating-gate cell and 3D vertical gate cell) [38,94,95], which are less common than the 3D charge trap NAND flash memory cell technology that we test in this paper. Other recent works [23,31,78,80,92] report several differences of 3D NAND flash memory from planar NAND flash memory. These differences include (1) smaller program variation at high P/E cycle counts [80], (2) smaller program interference [80], (3) layer-to-layer process variation [92], (4) early retention loss [23,31,78], and (5) retention interference [23].…”

Section: Related Workmentioning

confidence: 99%

“…Only one of these prior works [23] provides a detailed analysis based on circuitlevel measurements and characterizations, and does so only for early retention loss and retention interference. Other works provide only a high-level summary of real device characterization [80] or do not provide any real device characterization results at all [31,78,92]. Our work performs an extensive detailed analysis of all known sources of error in 3D NAND flash memory chips, which allows us to understand the relative impact of each error source on the same chip.…”

Section: Related Workmentioning

confidence: 99%

“…This, however, comes at the cost of lower reliability [9,13,69]. Due to a combination of manufacturing process technology limitations and reduced reliability of planar NAND flash memory, it has become increasingly difficult for vendors to continue to scale the density of planar NAND flash memory chips [11,31,80].…”

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confidence: 99%

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Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Luo

Ghose

Cai

et al. 2018

Proc. ACM Meas. Anal. Comput. Syst.

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Compared to planar (i.e., two-dimensional) NAND flash memory, 3D NAND flash memory uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip. This allows 3D NAND flash memory to increase storage density using a much less aggressive manufacturing process technology than planar NAND flash memory. The circuit-level and structural changes in 3D NAND flash memory significantly alter how different error sources affect the reliability of the memory.In this paper, through experimental characterization of real, state-of-the-art 3D NAND flash memory chips, we find that 3D NAND flash memory exhibits three new error sources that were not previously observed in planar NAND flash memory: (1) layer-to-layer process variation, a new phenomenon specific to the 3D nature of the device, where the average error rate of each 3D-stacked layer in a chip is significantly different; (2) early retention loss, a new phenomenon where the number of errors due to charge leakage increases quickly within several hours after programming; and (3) retention interference, a new phenomenon where the rate at which charge leaks from a flash cell is dependent on the data value stored in the neighboring cell.Based on our experimental results, we develop new analytical models of layer-to-layer process variation and retention loss in 3D NAND flash memory. Motivated by our new findings and models, we develop four new techniques to mitigate process variation and early retention loss in 3D NAND flash memory. Our first technique, Layer Variation Aware Reading (LaVAR), reduces the effect of layer-to-layer process variation by fine-tuning the read reference voltage separately for each layer. Our second technique, Layer-Interleaved Redundant Array of Independent Disks (LI-RAID), uses information about layer-to-layer process variation to intelligently group pages under the RAID error recovery technique in a manner that reduces the likelihood that the recovery of a group fails significantly earlier than the recovery of other groups. Our third technique, Retention Model Aware Reading (ReMAR), reduces retention errors in 3D NAND flash memory by tracking the retention time of the data using our new retention model and adapting the read reference voltage to data age. Our fourth technique, Retention Interference Aware Neighbor-Cell Assisted Correction (ReNAC), adapts the read reference voltage to the amount of retention interference a page has experienced, in order to re-read the data after a read operation fails. These four techniques are complementary, and can be combined together to significantly improve flash memory reliability. Compared to a state-of-the-art baseline, our techniques, when combined, improve flash memory lifetime by 1.85×. Alternatively, if a NAND flash vendor wants to keep the lifetime of the 3D NAND flash memory device constant, our techniques reduce the storage overhead required to hold error correction information by 78.9%.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

mentioning

confidence: 99%

See 2 more Smart Citations

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Luo

Ghose

Cai

et al. 2018

Proc. ACM Meas. Anal. Comput. Syst.

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“…The advent of three-dimensionally integrated NAND Flash (i.e., 3D NAND) [10] seemed to alleviate such a trade-off, but not the need for the DRAM to cope with the performance disparity between the host system and the SSD. Reliability is however still a concern [11].…”

Section: A Solid State Drives: the Limitations Of Nand Flashmentioning

confidence: 99%

Phase Change and Magnetic Memories for Solid-State Drive Applications

et al. 2017

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The state-of-the-art solid-state drives (SSDs) now heterogeneously integrate nand Flash and dynamic random access memories (DRAMs) to partially hide the limitation of the nonvolatile memory technology. However, due to the increased request for storage density coupled with performance that positions the storage tier closer to the latency of the processing elements, nand Flash are becoming a serious bottleneck. DRAM as well are a limitation in the SSD reliability due to their vulnerability to the power loss events. Several emerging memory technologies are candidate to replace them, namely the storage class memories. Phase change memories and magnetic memories fall into this category. In this work, we review both technologies from the perspective of their possible application in future disk drives, opening up new computation paradigms as well as improving the storage characteristics in terms of latency and reliability

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Conduction Mechanisms on High Retention Annealed MgO-based Resistive Switching Memory Devices

Loy

Dananjaya

Hong

et al. 2018

Sci Rep

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We report on the conduction mechanisms of novel Ru/MgO/Cu and Ru/MgO/Ta resistive switching memory (RSM) devices. Current-voltage (I–V) measurements revealed Schottky emission (SE) as the dominant conduction mechanism in the high resistance state (HRS), which was validated by varying temperatures and transmission electron microscopy (TEM) results. Retention of more than 10 years at 85 °C was obtained for both Ru/MgO/Ta and Ru/MgO/Cu RSM devices. In addition, annealing processes greatly improved the consistency of HRS and LRS switching paths from cycle to cycle, exhibiting an average ON/OFF ratio of 102. Further TEM studies also highlighted the difference in crystallinity between different materials in Ru/MgO/Cu RSM devices, confirming Cu filament identification which was found to be 10 nm in width.

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Reliability of 3D NAND Flash Memories

Cited by 13 publications

References 28 publications

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Phase Change and Magnetic Memories for Solid-State Drive Applications

Conduction Mechanisms on High Retention Annealed MgO-based Resistive Switching Memory Devices

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