Reliability of a QCA Array Multiplier

Abstract

Defects and faults of the future circuit technologies have to be taken into account early in the design of digital systems. To form practical design guidelines, we study the relationship between system reliability and component failure rates, in the case of a binary multiplier unit on quantumdot cellular automata nanotechnology. The analysis is based on a decomposition of probabilistic transfer matrices, a versatile framework for computing the conditional probability of system failure. Our results indicate that passive wiring dominates the reliability of arithmetic designs on the nanotechnology. I. INTRODUCTIONHigh defect rates in the manufacturing process and various dynamic faults occurring during the runtime operation determine the practicality of digital designs, implemented with the future circuit technologies: the primitive components function or fail with imperfect stochastic characteristics, instead of the traditional deterministic behavior. A component with non-zero failure rate affects the reliability of the complete system, but these relations are unknown for many important applications, making it difficult to aim the costly improvements to the target of most effect on the total reliability. Designers are tempted to adopt overkill solutions, with unjustifiable cost, possibly attacking the fault-tolerance on a wrong design level.This paper explores the reliability of binary multiplication, executed on a massively parallel array multiplier (AM) structure. We compare the contribution of the passive wiring and the active computing hardware in a layout level implementation, based on quantum-dot cellular automata (QCA) nanotechnology, which is one of the foremost candidates to replace transistor based digital technologies. The nanotechnology is expected to reach circuit densities and clock frequencies several decades higher than the technological peak of the complementary metal oxide semiconductor (CMOS) [1]. The concept was introduced in early 1990s, and has been demonstrated in with small proof-of-concept systems [2]- [4].Our analysis, based on the probabilistic transfer matrix (PTM) approach, shows that the total reliability of an array multiplier depends linearly on the failure rates of the macro components (passive wiring and active logic). The wire blocks dominate the total reliability, in comparison with the contribution of the actual computation logic (full adders and summand formation). The results are used in conjunction with the previous studies, to transform the architectural requirements into the failure rates of the low-level circuit primitives.The rest of this paper is organized as follows: Section II summarizes the previous research on QCA reliability, while