Reliability of PWB microvias for high density package assembly

Ghaffarian, Reza

doi:10.1504/ijmsi.2008.018900

Cited by 6 publications

(2 citation statements)

References 10 publications

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“…However, accompanying all of the advantages described above is a high occurrence rate of soldering defects, such as voids (Badaram, 2011;Ghaffarian, 2008;Grano et al, 2003;Harjinder and Sundar, 2003;Liu et al, 2011;Schwiebert, 1994;Singer et al, 2003) and extreme cases of tombstoning in the assembly of tiny passive components. Tombstoning is the lifting of one end of a leadless component, such as a capacitor or a resistor, and the standing on another of its ends, as shown in Figure 1.…”

Section: Introductionmentioning

confidence: 99%

The effect of micro via‐in pad designs on surface‐mount assembly defects: part I – tombstoning

Lee

Kim

Suganuma

2012

Soldering &Amp; Surface Mount Technology

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Purpose -To propose a solution procedure to minimize/eliminate tombstoning defects in small chip components with different micro via-in pad designs for high density module assembly. Design/methodology/approach -Four different micro via-in pad designs were compared (via-hole diameter): ultra small via-in pads (10 mm), small via-in pads (20 mm) and large via-in pads (60 mm), as well as designs with no via-in pads and capped via-in pads. Two process variables were also evaluated for the goal of achieving a high-yield assembly solution in micro via-in pad and lead-free solder conditions. Potential factors such as the preheat conditions of the reflow profile and stencil aperture size, which might affect tombstoning in components with micro via-in pads, were investigated. Findings -The results indicated that the micro via-in pad design significantly increased the tombstoning; thus, tombstoning did not occur in components with both no via-in pads and capped via-in pads. Capped via-in pads exhibited the best results in preventing tombstoning and provided a wide process window for the selection of process parameters. The results showed that tombstoning was found to decrease with both increasing stencil opening ratio and use of reflow profile with long-preheat condition. Originality/value -The paper's findings provide certain process guidelines for high density module assemblies with via-in pad design. The strategy is to prevent tombstoning by adopting capped via-in pad design if possible when employing micro via-in pad technology.

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Section: Introductionmentioning

confidence: 99%

The effect of micro via‐in pad designs on surface‐mount assembly defects: part I – tombstoning

Lee

Kim

Suganuma

2012

Soldering &Amp; Surface Mount Technology

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“…Extensive work has been carried out by industry and a number of consortia in order to understand technology implementation of AAPs for high-reliability applications. The work included process optimization, assembly reliability characterization, and the use of inspection tools, including X-ray and optical microscopy, for quality control and damage detection due to environmental exposures [2][3][4][5][6][7][8][9][10][11]. Figure 2 illustrates a few samples of electronic package assemblies from plated through-hole (PTH) to surface mount technologies (SMT) as well as recent package assemblies with plastic and ceramic BGAs.…”

Section: Introductionmentioning

confidence: 99%

Thermal Cycle and Vibration/Drop Reliability of Area Array Package Assemblies

Ghaffarian

2011

Structural Dynamics of Electronic and Photonic Systems

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SUMMARYCommercial off-the-shelf area array packaging (COTS AAP) technologies are considered for use in a number of high-reliability electronics systems. Understanding the process and quality assurance (QA) indicators for reliability, as well as developing methods to project life under thermal and mechanical environment, is important for the low-risk insertion of these newly available electronic packages. Extensive investigations were performed by NASA in collaboration with industry and universities to address key manufacturing and reliability issues on the continuously evolving AAP technology. The reliability results based on test data will facilitate use of various low-pitch and high-input/output (I/O) area array packages, with more processing power in a smaller board footprint. Topics discussed in this chapter are as follows:• Packaging technology trend for AAPs, including plastic ball grid array (PBGA), chipscale packages (CSPs), and 3D stack packages. • Summary of key parameters that affect assembly reliability of PBGAs and flip-chip BGA (FCBGA) based on a comprehensive literature search. The effect of a doublesided mirror image array package on solder joint reliability is also addressed. IPC 9701A specification was reviewed for lead-free solder alloy requirements. • Test results for a test vehicle having various packages including a PBGA with 1156 I/Os subjected to various thermal cycling. X-ray and scanning electron microscopy (SEM) and X-sections after thermal cycling. • Literature survey and test results for a COTS PBGA 676 I/O package assembly with various ball/solder alloys representing the current migration of industry to lead-free solders. A number of test vehicles, assembled and supplied by an engineering manufacturing service (EMS) company collaborator, were subjected to thermal cycling evaluation as part of collaboration activity. The test results are presented. • The test results for thermal cycling and vibration of numerous CSPs soldered with tin-lead and with and without underfill are presented. • Extensive vibration and thermal cycle data were generated by the consortium team members of the Joint Council on Aging Aircraft/Joint Group on Pollution Prevention (JCAA/JG-PP). Vibration test results for BGA 225 I/O package assemblies with tin-lead and lead-free solder were reviewed and compared with other models and 519

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Life assessment of Micro-via used in thin Printed Circuit Board under Thermal Cycling loads & influence of selected design parameters

Kumar,

Bhadri

2023

2023 IEEE 25th Electronics Packaging Technology Conference (EPTC)

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Reliability of PWB microvias for high density package assembly

Cited by 6 publications

References 10 publications

The effect of micro via‐in pad designs on surface‐mount assembly defects: part I – tombstoning

The effect of micro via‐in pad designs on surface‐mount assembly defects: part I – tombstoning

Thermal Cycle and Vibration/Drop Reliability of Area Array Package Assemblies

Life assessment of Micro-via used in thin Printed Circuit Board under Thermal Cycling loads & influence of selected design parameters

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