Reliability of soldered joints in CSPs of various designs and mounting conditions

Sumikawa, M.; Saza, Y.; Satô, Toshihiko; Yoshioka, C.; Rai, Akiteru; Nukii, Takashi

doi:10.1109/iemtim.1998.704627

Cited by 4 publications

(2 citation statements)

References 5 publications

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“…The Coffin-Manson equation predicts that the thermal fatigue lifetime of a solder joint is proportional to the square of the bump standoff (in the plastic deformation region) [5]. A greater bump standoff results in lower solder stress, but higher stress in the underlying structure [18]. More solder bumps at any given DNP will lower the overall stress by distributing it across the structure.…”

Section: Reliabilitymentioning

confidence: 99%

Wafer level chip scale packaging (WL-CSP): an overview

Garrou

2000

IEEE Trans. Adv. Packag.

174

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Several wafer level chip scale package (WLCSP) technologies have been developed which generate fully packaged and tested chips on the wafer prior to dicing. Many of these technologies are based on simple peripheral pad redistribution technology followed by attachment of 0.3-0.5 mm solder balls. The larger standoff generated by these solder balls result in better reliability for the WLCSP's when underfill is not used than for equivalent flip chip parts. Rambus™ RDRAM and integrated passives are two applications that should see wide acceptance of WLCSP packages.

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Section: Reliabilitymentioning

confidence: 99%

Wafer level chip scale packaging (WL-CSP): an overview

Garrou

2000

IEEE Trans. Adv. Packag.

174

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“…Sumikawa et. al reported that the size of a solder ball in a chip scale package is related to its vibration reliability [10]. Larger joints gave longer fatigue life.…”

Section: Introductionmentioning

confidence: 99%