Reliability of VLSI-level chip assembly for evaluating the development of back-end technologies using a test chip with a top two-level metal structure

Abstract

This paper investigates the effects of area and location of a chip, the material from which it is encapsulated, the geometry of the test structures, accelerated stressing operations and process technologies on the reliability of a VLSI-level chip assembly by using a 12 mm 12 mm large-die-size test chip with various top two-level metal test structures. The test chip is fabricated in a generic 0.18-m six-level AlCu-HSQ interconnect process and using specific dual-damascene Cu-FSG technology for top two-level metal. The proposed model is applied to analyze the failure distribution and identify the failure mechanism. The experimental results indicate that the mechanical and electrical performance of the assembled test chip, both of which depend strongly on back-end processes, can significantly impact the failure distribution and the failure mechanism in testing of the reliability of the chip assembly.Index Terms-Assembly reliability, CMOS, coefficients of thermal expansion (CTE), dual damascene, FSG, HSQ, intermetal dielectric (IMD), large-die-size chip, silicon in-package (SIP), system-on-chip (SOC), test chip, VLSI.