Reliable and ultra-low power approach for designing of logic circuits

Haq, Shams Ul; Sharma, Vijay Kumar

doi:10.1007/s10470-023-02207-2

Cited by 3 publications

(3 citation statements)

References 27 publications

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“…The VTC curves of the proposed SQI are steeper compared to the other designs. These steeper VTC curves lead to higher gain or higher slope causing the transitions regions to be smaller [76,77]. The short circuit path conducts current for a very short period compared to the other designs where besides having more than one short circuit paths, short circuit conduction time is higher due to their larger transition region.…”

Section: Comparison Analysismentioning

confidence: 99%

Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology

Haq,

Abbasian,

Khurshid

et al. 2024

Phys. Scr.

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Multi-valued logic (MVL), which is an extension of binary logic, is a framework for representing complex systems with more than two truth values. This paper delves into the circuit design, computational aspects, and practical applications of the quaternary logic system, which is a type of MVL with four truth values. The multi-threshold property of carbon nanotube field-effect-transistors (CNTFET), along with resistive random-access memory (RRAM) having the capability of storing multiple resistance values, has been used in the design of quaternary logic gates and arithmetic circuits. The non-volatility in the design achieved using RRAMs enables the circuits to be used in reconfigurable logic and in-memory computational applications. The properties of RRAM, like resistance switching and multi-cell storage, have been used to optimize the proposed circuits. Quaternary logic gates such as inverter, NAND, and NOR, and quaternary arithmetic circuits including decoder, half adder, and multiplier have been designed. The power-delay-product (PDP) of the proposed quaternary inverter, NAND, NOR, half adder, and multiplier is 62.38%, 93.4%, 80.29%, 14.79%, and 20% less than the least PDP of the quaternary designs under consideration, respectively.

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Section: Comparison Analysismentioning

confidence: 99%

Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology

Haq,

Abbasian,

Khurshid

et al. 2024

Phys. Scr.

Self Cite

View full text Add to dashboard Cite

show abstract

“…In the literature [8][9][10], device-or transistor-level optimisation is performed, and then these devices are used to implement different existing circuits. While some studies [11][12][13] focus on circuit-level optimization, our approach for performance optimization also includes a circuit-level approach.…”

Section: Introductionmentioning

confidence: 99%

INDIDO: A novel low-power approach for domino logic circuits

Mushtaq,

Akram,

Prasad

et al. 2024

Phys. Scr.

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Power dissipation in Nanoelectronic circuits at advanced technology nodes is dominated by leakage power dissipation. This is due to an increase in short channel effects in the scaled transistors. The VLSI industry is seeking alternative options to enhance the performance of portable electronic systems by ensuring higher speed and reduced power dissipation. In the ultra-deep submicron (DSM) regime, a new device called the fin-shaped field effect transistor (FinFET) was developed to replace CMOS technology. FinFET, a multi-gate device, significantly reduces power dissipation compared to planer MOS (Metal Oxide Semiconductor ) transistor, but it doesn't entirely resolve the issue. To further reduce power dissipation in the ultra DSM regime, low power approaches are required. Domino logic, a widely-used dynamic logic, is commonly utilized in high-speed VLSI architectures. In this research work, a novel INput Dependent Inverter DOmino (INDIDO) logic approach for low-power domino logic circuits using FinFET devices is proposed. A comparative analysis between the proposed INDIDO method and the existing approaches is performed for domino logic circuits for various performance metrics at the 16 nm technology node. In this research, various circuits like domino buffer, domino OR, domino AND, domino XOR and domino half adder are designed using the proposed INDIDO approach. The proposed INDIDO FinFET buffer circuit offers significant improvement in energy efficiency and FOM (Figure of Merit) by 53.18 % and 82% respectively as compared to conventional FinFET footed domino buffer circuit. Beside this, proposed circuits like INDIDO OR, INDIDO AND, INDIDO XOR and INDIDO Half adder circuit follow the same trend as INDIDO buffer circuit and show better performance parameters in comparison to the existing low power domino approaches as well. In addition to this, the proposed INDIDO buffer circuits are also analyzed for PVT(process voltage and temperature) variability. This whole analysis makes us to conclude that proposed INDIDO approach reduces power dissipation and delay penalty, have high noise tolerance capacity, more immunity against PVT variations and high energy efficiency in comparison to the already existing techniques.

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“…Scaling is the most important factor in VLSI circuits due to the excessive number of gadgets built on a chip to make the circuit cheaper and faster. The reduction of the size of transistors creates serious issues in electronics systems such as leakage current, reliability degradation, increased power dissipation, and SCEs [4,5].…”

Section: Introductionmentioning

confidence: 99%

Circuits implementations using carbon nanotube field-effect transistor nanotechnology

Maqbool,

Sharma

2024

Eng. Res. Express

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Device scaling is a pivotal aspect in the field of electronics, aimed at enhancing the performance of integrated circuits (ICs) by reducing the dimensions of transistors. The device scaling presents the short channel effects (SCEs) in the nanoscale regime. To address the SCEs, nanometer IC designers have turned to the carbon nanotube field-effect transistor (CNTFET) technology, which offers unique properties and mitigates the challenges associated with transistor scaling. In this research work, a leakage reduction technique known as the input-dependent (INDEP) method is suggested to tackle the leakage current issue at the nanoscale regime using CNTFET technology. The INDEP method involves the incorporation of two additional transistors within the logic circuit. To evaluate the efficacy of the INDEP method, a CNTFET-based 7-stage inverter chain is meticulously designed at 32 nm CNTFET technology node. Subsequent comparative analysis against alternative designs is conducted, assessing performance metrics such as power dissipation, delay, and power delay product (PDP). The suggested INDEP method reduces power dissipation by 83.75% and improves PDP by 78.44%. Furthermore, the study delves into the impact of process, voltage, and temperature (PVT) variations. Additionally, the investigation explores the influence of parameters such as the number of carbon nanotubes, temperature, supply voltage, and chiral indices on the performance of the 7-stage inverter chain. The simulation results demonstrate that the CNTFET-based INDEP technique yields promising outcomes, characterized by low power dissipation, precise output, and minimal uncertainty across all evaluated metrics.

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Reliable and ultra-low power approach for designing of logic circuits

Cited by 3 publications

References 27 publications

Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology

Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology

INDIDO: A novel low-power approach for domino logic circuits

Circuits implementations using carbon nanotube field-effect transistor nanotechnology

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