Reliable Computing with Ultra-Reduced Instruction Set Coprocessors

Wang, Dan; Rajendiran, Aravindkumar; Ananthanarayanan, Sundaram; Patel, Hiren; Tripunitara, Mahesh; Garg, Siddharth

doi:10.1109/mm.2013.130

Cited by 4 publications

(1 citation statement)

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“…At the same time, as the entire platform still supports the fullfledged ISA, instruction sequences not prone to approximation can still run at full accuracy. AISC can also be regarded as an aggressive variant of architectural core salvaging [13] or ultrareduced instruction set coprocessors [20], where actual hardware faults impair a compute engine's capability to implement a subset of its ISA (and all compute engines support the same ISA by design). These lines of studies detail how to achieve full-fledged functional completeness under the hardware-faultinduced loss of support for a subset of instructions.…”

Section: Introductionmentioning

confidence: 99%

AISC: Approximate Instruction Set Computer

Ferreron,

Alastruey-Benede,

Suarez-Gracia

et al. 2018

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This paper makes the case for a single-ISA heterogeneous computing platform, AISC, where each compute engine (be it a core or an accelerator) supports a different subset of the very same ISA. An ISA subset may not be functionally complete, but the union of the (per compute engine) subsets renders a functionally complete, platform-wide single ISA. Tailoring the microarchitecture of each compute engine to the subset of the ISA that it supports can easily reduce hardware complexity. At the same time, the energy efficiency of computing can improve by exploiting algorithmic noise tolerance: by mapping code sequences that can tolerate (any potential inaccuracy induced by) the incomplete ISA-subsets to the corresponding compute engines.

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Section: Introductionmentioning

confidence: 99%