Reliable processing of graphene using metal etchmasks

Kumar, Sunil; Peltekis, N.; Lee, Kangho; Kim, Hye-Young; Duesberg, Georg S.

doi:10.1186/1556-276x-6-390

Cited by 39 publications

(39 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Furthermore Fig. 4b shows the corresponding output characteristic which exhibits the typical three region behavior of a large area monolayer graphene transistor as described in [23], confirming the existence of transfer-free and in-situ CCVD grown and [24] as well as in our work.…”

Section: B Electrical Characterizationsupporting

confidence: 67%

Transfer-free fabrication of graphene transistors

Wessely

Birinci

et al. 2012

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

View full text Add to dashboard Cite

We invented a method to fabricate graphene transistors on oxidized silicon wafers without the need to transfer graphene layers. To stimulate the growth of graphene layers on oxidized silicon a catalyst system of nanometer thin aluminum/nickel double layer is used. This catalyst system is structured via liftoff before the wafer enters the catalytic chemical vapor deposition (CCVD) chamber. In the subsequent methane based growth process monolayer graphene field-effect transistors (MoLGFETs) and bilayer graphene transistors (BiLGFETs) are realized directly on oxidized silicon substrate, whereby the number of stacked graphene layers is determined by the selected CCVD process parameters, e.g. temperature and gas mixture. Subsequently, Raman spectroscopy is performed within the channel region in between the catalytic areas and the Raman spectra of fivelayer, bilayer and monolayer graphene confirm the existence of graphene grown by this silicon-compatible, transfer-free and in-situ fabrication approach. These graphene FETs will allow a simple and low-cost integration of graphene devices for nanoelectronic applications in a hybrid silicon CMOS environment.2

show abstract

Section: B Electrical Characterizationsupporting

confidence: 67%

Transfer-free fabrication of graphene transistors

Wessely

Birinci

et al. 2012

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

View full text Add to dashboard Cite

show abstract

“…Changing the sweep direction shifts the Dirac point from V BG = -6V to V BG = 11V which is equivalent to a hysteresis of ΔV BG = 17 V. Lemme [6] reports a hysteresis of ΔV BG = 22 V for a front gated MoLGFET on silicon dioxide substrate. Top contacted graphene ribbons on Al 2 O 3 substrate are examined by Kumar et al [7], exhibiting a hysteresis of ΔV BG ~ 20 V. Wang et al [8] show current voltage characteristics exhibiting a positive hysteresis of the same order of magnitude as found in both [6] and [7]. Fig.…”

Section: Resultsmentioning

confidence: 99%

In Situ CCVD Grown Bilayer Graphene Transistor

Wessely

Birinci

et al. 2012

ECS Trans.

View full text Add to dashboard Cite

In this paper we report on a novel method to fabricate graphene transistors directly on oxidized silicon wafers without the need to transfer graphene. By means of catalytic chemical vapor deposition (CCVD) the in-situ grown monolayer graphene field-effect transistors (MoLGFETs) and bilayer graphene field-effect transistors (BiLGFETs) are realized directly on oxidized silicon substrate. In-situ CCVD grown MoLGFETs exhibit the expected Dirac point together with the typical low on/off-current ratios of 16. In addition, however, in-situ CCVD grown BiLGFETs possess unipolar p-type device characteristics with an extremely high on/off-current ratio up to 1x10 7 exceeding previously reported values by several orders of magnitude. With this novel fabrication method hundreds of large scale in-situ CCVD grown graphene FETs are realized simultaneously on one 2'' wafer. Besides the excellent device characteristics, the complete CCVD fabrication process is silicon CMOS compatible. This will allow a simple and low-cost integration of graphene devices for nanoelectronic applications in a hybrid silicon CMOS environment.

show abstract

“…Furthermore, since single-layer graphene is oneatom thick, any residues from fabrication can significantly influence charge transport and electronic device performance. [11][12][13][14][15][16] Although several studies have reported dry etching procedures for graphene-based devices, [17][18][19][20][21][22][23][24][25] this previous work primarily employed optical microscopy and Raman spectroscopy to determine optimal etching conditions. While these methods provide valuable information, they lack sufficient resolution and/or sensitivity to definitively detect residual graphene and/or etching byproducts at the nanoscale.…”

Section: Manuscriptmentioning

confidence: 99%

Optimization of graphene dry etching conditions via combined microscopic and spectroscopic analysis

Prado

Jariwala²,

Marks

et al. 2013

Applied Physics Letters

View full text Add to dashboard Cite

Single-layer graphene structures and devices are commonly defined using reactive ion etching and plasma etching with O 2 or Ar as the gaseous etchants. Although optical microscopy and Raman spectroscopy are widely used to determine the appropriate duration of dry etching, additional characterization with atomic force microscopy (AFM) reveals that residual graphene and/or etching byproducts persist beyond the point where the aforementioned methods suggest complete graphene etching. Recognizing that incomplete etching may have deleterious effects on devices and/or downstream processing, AFM characterization is used here to determine optimal etching conditions that eliminate graphene dry etching residues.

show abstract

Reliable processing of graphene using metal etchmasks

Cited by 39 publications

References 11 publications

Transfer-free fabrication of graphene transistors

Transfer-free fabrication of graphene transistors

In Situ CCVD Grown Bilayer Graphene Transistor

Optimization of graphene dry etching conditions via combined microscopic and spectroscopic analysis

Contact Info

Product

Resources

About