Reliable synchronization accuracy in ieee 1588 networks using device qualification with standard test patterns

Flatt, Holger; Schriegel, Sebastian; Jasperneite, Jürgen

doi:10.1109/ispcs.2013.6644772

Cited by 7 publications

(2 citation statements)

References 11 publications

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“…In comparison with the forwarding mode of the transparent clock where the correction fields are unfilled and the average delay between the nodes is between 15-16 us, here the majority of the sync delay is between 5-7 milliseconds in all cases. These measurements are in sync with some other experiments [8]. Despite the high latency, the examination of the slave nodes offset (PPS signal) shows that the jitter of these measurements is low.…”

Section: B Measurement Resultssupporting

confidence: 84%

One-way delay measurement system for local area network delay and jitter characterization

Ferencz

Kovácsházy

2014

Proceedings of the 2014 15th International Carpathian Control Conference (ICCC)

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The IEEE 1588 Standard for A Precision Clock Synchronization Protocol for Networked Measurement and Control Systems (PTP) has been developed to provide better quality in-band clock synchronization in distributed measurement and control systems and other network embedded systems. Using IEEE 1588 compliant Ethernet equipment (network interface cards and switches) it is possible to provide sub 1 microsecond precision of slave clocks compared to a reference clock. The centerpiece of an IEEE 1588 based clock is the clock servo disciplining the local clock based on the information provided by IEEE 1588 about the reference time. However, it is an opened question how precision can be increased even further by advanced clock servo design. Furthermore, as only a minority of office and industrial Ethernet switches support IEEE 1588, it is also paramount to investigate the achievable performance for such systems, which is also defined by the clock servo.To design advanced control systems the plant and the disturbances must be modeled, and the model must be built based on representative measurements. In our case, the one-way network delay in between the reference clock and the slave clock must be characterized in Local Area Networks (LAN) for typical network load scenarios for advanced servo design, so 1-10 ns accurate one-way delay and jitter measurements must be achieved for this application. Measuring one-way delay in Local Area Networks requires specialized and expensive equipment; however, we will show that it is possible to build such measurement system using commercial off-the-shelf (COTS) components and open source software. Our system uses Intel network interface cards, the open source Linux operating system, and some self-developed software components (both Linux kernel drivers and user space programs).

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Section: B Measurement Resultssupporting

confidence: 84%

One-way delay measurement system for local area network delay and jitter characterization

Ferencz

Kovácsházy

2014

Proceedings of the 2014 15th International Carpathian Control Conference (ICCC)

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“…Recently, the topic of synchronization in network nodes has attracted significant attention for a number of applications [1][2][3][4][5][6][7][8][9][10]. In many cases the global positioning system (GPS) is used to synchronize frequency and time accuracy in the sub-microsecond range.…”

Section: Introductionmentioning

confidence: 99%

Maximum Likelihood Estimation of Clock Skew in IEEE 1588 with Fractional Gaussian Noise

Levy

Pinchas

2015

Mathematical Problems in Engineering

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To support system-wide synchronization accuracy and precision in the sub-microsecond range without using GPS technique, the precise time protocol (PTP) standard IEEE-1588 v2 is chosen. Recently, a new clock skew estimation technique was proposed for the slave based on a dual slave clock method that assumes that the packet delay variation (PDV) in the Ethernet network is a constant delay. However, papers dealing with the Ethernet network have shown that this PDV is a long range dependency (LRD) process which may be modeled as a fractional Gaussian noise (fGn) with Hurst exponent (H) in the range of0.5<H<1. In this paper, we propose a new clock skew estimator based on the maximum likelihood (ML) technique and derive an approximated expression for the Cramer-Rao lower bound (CRLB) both valid for the case where the PDV is modeled as fGn (0.5<H<1). Simulation results indicate that our new clock skew method outperforms the dual slave clock approach and that the simulated mean square error (MSE) obtained by our new proposed clock skew estimator approaches asymptotically the developed CRLB.

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Reliable comparison of clock discipline algorithms for time synchronization protocols

Cena

Scanzio

Valenzano

2015

2015 IEEE 20th Conference on Emerging Technologies &Amp; Factory Automation (ETFA)

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Reliable synchronization accuracy in ieee 1588 networks using device qualification with standard test patterns

Cited by 7 publications

References 11 publications

One-way delay measurement system for local area network delay and jitter characterization

One-way delay measurement system for local area network delay and jitter characterization

Maximum Likelihood Estimation of Clock Skew in IEEE 1588 with Fractional Gaussian Noise

Reliable comparison of clock discipline algorithms for time synchronization protocols

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