reMORPH: A Runtime Reconfigurable Architecture

Abstract

Programmable hardware built on a regular architecture can partially alleviate the problem of increased defect densities associated with transistor scaling by dynamically wiring around the defects [1]. The fine granularity of FPGAs is however unsuitable for effectively exploiting runtime reconfiguration because of the high overheads involved. A coarse grain reconfigurable array with malleable communication links -reMORPH -is proposed in this paper. The compute tile uses DSP48E and BRAM embedded blocks in a Xilinx FPGA and has a very low footprint of about 200 slice LUTs. The semi-systolic near neighbour communication interconnect can be dynamically reconfigured for each "epoch" of computation. The "epoch" or phases of the application are obtained via profiling or static data flow analysis. Some of the links between the compute tiles are changed during the reconfiguration phase which drastically reduces the context switch overhead enabling high performance/area applications to be built on this fabric.

A time-multiplexed FPGA overlay with linear interconnect

“…An alternative solution is to build arrays of customized TM FUs and interconnect on the FPGA, similar to CGRAs [17]. A number of different interconnect styles for connecting between FUs can be used, with the most common being: island style [6], [8], nearest neighbor [20], [16] and to a lesser extent linear interconnect [3], [9]. The overhead of the interconnect network, particularly for island style and nearest neighbor interconnects, contribute to a significant FPGA resource utilization.…”

“…The reMORPH overlay [20] better targets the FPGA fabric, with an FU consuming 1 DSP Block, 3 block RAMs, 196 LUTs and 41 registers. To reduce overhead, the reMORPH FU does not use decoders resulting in a 72-bit instruction memory (supporting up to 512 instructions) which also over utilizes the BRAMs.…”

“…NOPs (equal to IWP-1) must be added between dependant instructions (DFG nodes) unless other non-dependant instructions can be scheduled in between. For example, in the first (top) cluster, Node 17 is scheduled, followed by 13,25,9,20, and 12, before 15 is scheduled. Hence, the dependency between 17 and 15 is resolved and no NOPs are inserted.…”

High performance 3D-FFT implementation

“…Paul et al have reported that if the reconfiguration is limited to changing the connectivity at runtime, the overheads are typically very low [1]. This allows fairly large circuits to be implemented modularly in a time multiplexed manner which makes the implementation area and power efficient.…”

“…reMORPH [1] is a reconfigurable nearest neighbor mesh connected array of coarse grain reconfigurable tiles as illustrated in Figure 2. Modern FPGAs have hard DSP macros and lots of embedded memory which have been used to design the processing element (PE) to operate at 400 MHz with a very low footprint of 200 slice LUTs.…”