Repairing and mechanising the JavaScript relaxed memory model

Watt, Conrad; Pulte, Christopher; Podkopaev, Anton; Barbier, Guillaume; Dolan, Stephen K.; Flur, Shaked; Pichon-Pharabod, Jean; Guo, Shuyu

doi:10.1145/3385412.3385973

Cited by 12 publications

(15 citation statements)

References 33 publications

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“…The work of Watt et al [43] predates neither the original Arm model nor the upstreaming of the Armv8 mixed-size model introduced in the present article [6]. It does, however, set out to build "a novel mixed-size ARMv8 axiomatic model, as a generalisation of ARM's axiomatic reference model, and validate it with respect to [.…”

Section: :7mentioning

confidence: 97%

“…No semantics nor implementation is given to those new cat constructs. 2020 [43] A mixed-size extension of the Armv8 model to handle mixed-size accesses, in Alloy and Coq. Appears to coincide with the original Arm guarantees given in Figure 18, which are too weak to program with-therefore the results in Reference [43] might be quite a bit stricter than necessary.…”

Section: :7mentioning

confidence: 99%

“…2020 [43] A mixed-size extension of the Armv8 model to handle mixed-size accesses, in Alloy and Coq. Appears to coincide with the original Arm guarantees given in Figure 18, which are too weak to program with-therefore the results in Reference [43] might be quite a bit stricter than necessary. 2020 [29] captures Arm-style MCA execution at the language level (including compiler optimizations).…”

Section: :7mentioning

confidence: 99%

“…Two existing works are concerned with mixed-size accesses in the context of Arm's consistency model [25,43].…”

Section: :7mentioning

confidence: 99%

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Armed Cats

Alglave

Deacon²,

Grisenthwaite³

et al. 2021

ACM Trans. Program. Lang. Syst.

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We report on the process for formal concurrency modelling at Arm. An initial formal consistency model of the Arm achitecture, written in the cat language, was published and upstreamed to the herd+diy tool suite in 2017. Since then, we have extended the original model with extra features, for example, mixed-size accesses, and produced two provably equivalent alternative formulations. In this article, we present a comprehensive review of work done at Arm on the consistency model. Along the way, we also show that our principle for handling mixed-size accesses applies to x86: We confirm this via vast experimental campaigns. We also show that our alternative formulations are applicable to any model phrased in a style similar to the one chosen by Arm.

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Section: :7mentioning

confidence: 97%

Section: :7mentioning

confidence: 99%

Section: :7mentioning

confidence: 99%

“…Two existing works are concerned with mixed-size accesses in the context of Arm's consistency model [25,43].…”

Section: :7mentioning

confidence: 99%

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Armed Cats

Alglave

Deacon²,

Grisenthwaite³

et al. 2021

ACM Trans. Program. Lang. Syst.

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“…In contrast, it is quite challenging to support MF in declarative (a.k.a. axiomatic) models, which have become the norm for hardware architectures (x86-TSO [Owens et al 2009], Power [Alglave et al 2014], Arm [Pulte et al 2017]) and programming languages (e.g., RC11 [Lahav et al 2017], OCaml [Dolan et al 2018], JavaAtomics [Bender and Palsberg 2019], Javascript [Watt et al 2020], WebAssembly [Watt et al 2019]) alike. In these models, there are no explicit write propagation transitions so that MF could require them to eventually take place.…”

Section: Introductionmentioning

confidence: 99%

Making weak memory models fair

Lahav

Namakonov

Oberhauser

et al. 2021

Proc. ACM Program. Lang.

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Liveness properties, such as termination, of even the simplest shared-memory concurrent programs under sequential consistency typically require some fairness assumptions about the scheduler. Under weak memory models, we observe that the standard notions of thread fairness are insufficient, and an additional fairness property, which we call memory fairness, is needed. In this paper, we propose a uniform definition for memory fairness that can be integrated into any declarative memory model enforcing acyclicity of the union of the program order and the reads-from relation. For the well-known models, SC, x86-TSO, RA, and StrongCOH, that have equivalent operational and declarative presentations, we show that our declarative memory fairness condition is equivalent to an intuitive model-specific operational notion of memory fairness, which requires the memory system to fairly execute its internal propagation steps. Our fairness condition preserves the correctness of local transformations and the compilation scheme from RC11 to x86-TSO, and also enables the first formal proofs of termination of mutual exclusion lock implementations under declarative weak memory models.

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