Repetitive model refactoring strategy for the design space exploration of intensive signal processing applications

Glitia, Calin; Boulet, Pierre; Lenormand, Eric; Barreteau, Michel

doi:10.1016/j.sysarc.2010.12.002

Cited by 14 publications

(7 citation statements)

References 10 publications

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“…The refactoring tool is used to discover the good quality trade-offs in the usage of storage, computation resources of signal processing applications [13]. The graph based relevance measure is used to find the various relations and rules between information resources [32].…”

Section: Related Workmentioning

confidence: 99%

Implication of Clone Detection and Refactoring Techniques using Delayed Duplicate Detection Refactoring

Deepika¹,

Sarala²

2014

IJCA

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Code maintenance has been increased when the similar code fragments is reduced in the software systems. Refactoring is a change made to the internal structure of software to make it easier to understand and cheaper to modify without changing its observable behavior based on code, the refactoring mechanism is used to discover the clone detection. The proposed algorithm insists semantic relevance between files, classes and methods towards c# applications. The delayed duplicate detection refactoring technique uses the code analyzer and semantic graph for quickly detect the duplicate files in the application. The implemented clone refactoring technique enhances the Semantic Relevance Entity Detection algorithm which provides better performance and accurate result for unifying the process of clone detection and refactoring.

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Section: Related Workmentioning

confidence: 99%

Implication of Clone Detection and Refactoring Techniques using Delayed Duplicate Detection Refactoring

Deepika¹,

Sarala²

2014

IJCA

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“…An Array-OL application specification [7] involves a set of tasks that can be elementary, compound or repeated. For our method, the repeated tasks are of main interest.…”

Section: A Application Specificationmentioning

confidence: 99%

“…Our method and tool exploit an application model, called Array-OL [7], which can be analyzed as a multidimensional SDF model [8] for static scheduling, but Array-OL is more suitable than SDF to efficiently describe data-oriented loop transformations [7]. Our method explores different loop transformations for an application with multiple communicating nested loops.…”

Section: Introductionmentioning

confidence: 99%

Design space exploration in application-specific hardware synthesis for multiple communicating nested loops

Corvino

Gamatié

Geilen

et al. 2012

2012 International Conference on Embedded Computer Systems (SAMOS)

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Abstract-Application specific MPSoCs are often used to implement high-performance data-intensive applications. MPSoC design requires a rapid and efficient exploration of the hardware architecture possibilities to adequately orchestrate the data distribution and architecture of parallel MPSoC computing resources. Behavioral specifications of data-intensive applications are usually given in the form of a loop-based sequential code, which requires parallelization and task scheduling for an efficient MPSoC implementation. Existing approaches in application specific hardware synthesis, use loop transformations to efficiently parallelize single nested loops and use Synchronous Data Flows to statically schedule and balance the data production and consumption of multiple communicating loops. This creates a separation between data and task parallelism analyses, which can reduce the possibilities for throughput optimization in high-performance data-intensive applications. This paper proposes a method for a concurrent exploration of data and task parallelism when using loop transformations to optimize data transfer and storage mechanisms for both single and multiple communicating nested loops. This method provides orchestrated application specific decisions on communication architecture, memory hierarchy and computing resource parallelism. It is computationally efficient and produces high-performance architectures.

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“…The input specification of the customization flow is given in an Array Oriented Language (ARRAY-OL) [17] that specifies all the information on task and data dependencies of the application needed for the application specific hardware synthesis. Indeed, an ARRAY-OL model instance contains two levels of abstractions for the application description.…”

Section: A Application Modelmentioning

confidence: 99%

Transformation-Based Exploration of Data Parallel Architecture for Customizable Hardware: A JPEG Encoder Case Study

Corvino

Diken

Gamatié

et al. 2012

2012 15th Euromicro Conference on Digital System Design

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Abstract-In this paper, we present a method for the design of MPSoCs for complex data-intensive applications. This method aims at a blend exploration of the communication, the memory system architecture and the computation resource parallelism. The proposed method is exemplified on a JPEG Encoder case study by describing all the design steps. Our method allows for a JPEG encoder implementation having a throughput increase of 84% and an increase of the achievable FPGA maximum frequency fmax of 64% with an area overhead of 6× with respect to a reference solution. Our method is also assessed with additional explorations of applications from different domains.

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Repetitive model refactoring strategy for the design space exploration of intensive signal processing applications

Cited by 14 publications

References 10 publications

Implication of Clone Detection and Refactoring Techniques using Delayed Duplicate Detection Refactoring

Implication of Clone Detection and Refactoring Techniques using Delayed Duplicate Detection Refactoring

Design space exploration in application-specific hardware synthesis for multiple communicating nested loops

Transformation-Based Exploration of Data Parallel Architecture for Customizable Hardware: A JPEG Encoder Case Study

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