Replica bit-line technique for embedded multilevel gain-cell DRAM

Abstract

Abstract-Multilevel gain-cell DRAMs are interesting to improve the area-efficiency of modern fault-tolerant systems-onchip implemented in deep-submicron CMOS technologies. This paper addresses the problem of long access times in such multilevel gain-cell DRAMs, which are further aggravated by process parameter variations. A replica bit-line (BL) technique, previously proposed for SRAM, is adapted to speed up the multilevel read operation at a negligible area-increase. Moreover, the same replica column is used to improve the write access time. An 8-kb DRAM macro implemented in 90-nm CMOS technology shows that the replica column is able to successfully track die-to-die process, voltage, and temperature variations to generate control signals with optimum delay. Finally, MonteCarlo simulations show that a small timing margin of 100 ps is sufficient to also cope with within-die process variations.

Review and classification of gain cell eDRAM implementations

“…Besides safely skipping power-hungry refresh cycles and designing for low retention times, the work in [8,21] also exploits the fact that wireless communications systems and other fault-tolerant systems are inherently resilient to a small number of hardware defects. In fact, by proposing memories based on multilevel GCs, the storage density of GC memories is further increased at the price of a small number of read failures which do not significantly impede the system performance [8,21].…”

“…Most memories designed for wireless communications systems or generally for SoCs still achieve bandwidths between 1 and 10 Gb/s. Only the high-density multilevel GC array has a lower bandwidth due to a slow successive approximation multilevel read operation [21]. GC memories targeted towards biomedical systems are preferably implemented in a mature, reliable 180 nm CMOS node and achieve sufficiently high bandwidths between 10 Mb/s and several 100 Mb/s at NVT or sub-V T supply voltages.…”

“…The common feature for all these circuits is their reduced device count, as compared to traditional SRAM circuits. The highest device count appears in [13], comprising three transistors and a gated diode, with all other proposals made up of two [3,5,11,15,18,19,22] or three [2,[8][9][10]12,14,20,21,24] transistors. The obvious implication of the transistor count is the bitcell size; however, the choice of the topology is application dependent, as well.…”

“…Using a same-type device for MR of a 2T cell induces an additional step in the same direction during read access, further impeding the performance. A hybrid cell, mixing NMOS and PMOS devices [3,8,10,19,21], can be used to combat these effects at the expense of in-bit well separation.…”

“…A few recent publications design and optimize GC memories for use in wireless communications systems or other fault-tolerant systems, while other work has verified the feasibility of lowvoltage operation, making GC arrays good candidates for biomedical systems. [2,3,5,[8][9][10][11][12][13][14][15][16][17][18][19][20][21].…”