Research and Design of Asynchronous FIFO Based on FPGA

Abstract

In this article, a design method of asynchronous FIFO memory based on FPGA is put forward. With FPGA as the core controller, We adopt Verilog HDL and top-down design method to build a top-level module design and also analyze the mark logic of asynchronous FIFO and the elimination of semi-stable state under Quartus II development platform. Besides, with the application of Gray code conversion technology, not only the reliable transmission of data is guaranteed but also design efficiency is improved. Through contrast experiment analysis and simulation test, the validity and reliability of asynchronous FIFO memory are verified, meeting the basic requirement that FIFO can hold more enough data without spillovers despite the fullness of data.

Optimization of Asynchronous FIFO Design Difficulties Using Verilog HDL

“…The write-full flag is a signal transmitted by the status circuit of FIFO when the FIFO is full or about to be full, to restrain the write operation of FIFO from continuing to write data into FIFO, resulting in overflow [6]. The read-empty flag is a signal transmitted by the status circuit of the FIFO when the FIFO is empty or about to be empty, to prevent the read operation of the FIFO from continuing to read data from the FIFO, resulting in the underflow.…”

Bit-Width Conversion Based on Asynchronous FIFO

“…So here the advantage of switching to Gray's code comes into play. Since there is only a 1-bit difference between two adjacent numbers, only 1 bit of the pointer will change when the pointer changes, while for natural binary numbers, there will be a number of simultaneous changes, for example, 0111 plus 1 becomes 1000, so all the bits change, so the probability of sub-stability is greatly reduced compared to natural binary numbers [6]. In addition, because the signal between 0 and 1 picked up by the sub-stable state will eventually become 0 or 1, for the gray code is to complete the expected change or not, for example: 0011->0010, if the final stable to 0, then the expected jump is completed; if stable to 1, then no change will occur, then the pointer will not move, which does not cause much impact, at most, will only lead to the appearance of false empty or false full situation.…”