2016
DOI: 10.1002/cpe.4042
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Research and implementation of a high performance parallel computing digital down converter on graphics processing unit

Abstract: Summary Digital down converter (DDC) is a time‐intensive and data‐intensive computing task and considered as the key technology in software defined radio. This paper proposes a high‐performance implementation of DDC on a graphics processing unit (GPU) using CUDA, which is composed of a numerically controlled oscillator stage, a cascaded integrator‐comb (CIC) decimation filter stage, and a finite impulse response (FIR) filter stage. The GPU implementation and optimizing of all the stages are studied in detail. … Show more

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Cited by 2 publications
(2 citation statements)
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“…In this study, the DDC process is examined in detail in the graphic processor; NCO, CIC, and finite impulse response (FIR) filtering process steps are mentioned . It is aimed to achieve large length data from small length data by segmenting CIC and FIR filtering operations.…”
Section: Related Workmentioning
confidence: 99%
See 1 more Smart Citation
“…In this study, the DDC process is examined in detail in the graphic processor; NCO, CIC, and finite impulse response (FIR) filtering process steps are mentioned . It is aimed to achieve large length data from small length data by segmenting CIC and FIR filtering operations.…”
Section: Related Workmentioning
confidence: 99%
“…Other than comparison with parallel CPU versions, we also compared our results to the paper that has the best results using DDC algorithm, which is Shaoi's work. In that work, The performance of our proposed DDC algorithm with respect to Shaoi's performance results 14 the author used NVIDIA Tesla K40 that has 2496 CUDA Cores for DDC algorithm. We use NVIDIA Quadro 1280 CUDA Cores as the most powerful GPUs.…”
Section: The Comparative Performance Evaluation Of Related Work and Pmentioning
confidence: 99%