Research of Wafer Level Bonding Process Based on Cu–Sn Eutectic

Wu, Daowei; Tian, Wenchao; Wang, Chuqiao; Huo, Ruixia; Wang, Yongkun

doi:10.3390/mi11090789

Cited by 13 publications

(8 citation statements)

References 22 publications

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“…TSV-based 3D stacking technology is proven to enable very-high-bandwidth and low-latency memory processor interconnects [ 42 ], and the resulting system is well suited for high throughput applications. For example, Kgil et al proposed a server called PicoServer, which utilizes 3D stacking to interstack a logic chip with multiple DRAM memory chips [ 43 ], as shown in Figure 6 .…”

Section: Chiplet-based Processing-in-memory Architecturementioning

confidence: 99%

Using Chiplet Encapsulation Technology to Achieve Processing-in-Memory Functions

Tian

Zhao

et al. 2022

Micromachines

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With the rapid development of 5G, artificial intelligence (AI), and high-performance computing (HPC), there is a huge increase in the data exchanged between the processor and memory. However, the “storage wall” caused by the von Neumann architecture severely limits the computational performance of the system. To efficiently process such large amounts of data and break up the “storage wall”, it is necessary to develop processing-in-memory (PIM) technology. Chiplet combines processor cores and memory chips with advanced packaging technologies, such as 2.5D, 3 dimensions (3D), and fan-out packaging. This improves the quality and bandwidth of signal transmission and alleviates the “storage wall” problem. This paper reviews the Chiplet packaging technology that has achieved the function of PIM in recent years and analyzes some of its application results. First, the research status and development direction of PIM are presented and summarized. Second, the Chiplet packaging technologies that can realize the function of PIM are introduced, which are divided into 2.5D, 3D packaging, and fan-out packaging according to their physical form. Further, the form and characteristics of their implementation of PIM are summarized. Finally, this paper is concluded, and the future development of Chiplet in the field of PIM is discussed.

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Section: Chiplet-based Processing-in-memory Architecturementioning

confidence: 99%

Using Chiplet Encapsulation Technology to Achieve Processing-in-Memory Functions

Tian

Zhao

et al. 2022

Micromachines

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“…In the case of the bonding layer, plating and deposition processes have been applied using various binary materials, such as Au-Sn, Cu-Sn, etc., and low-temperature processes and low-priced bonding materials are needed for mass production [ 5 , 6 ]. Recently, Cu-Sn, which is relatively cheap, has been widely used, and various thermal treatment methods in which microstructures were obtained have been reported, leading to increases in reliability [ 7 , 8 , 9 , 10 , 11 , 12 ]. Kumar S. et al reports Matano plane-based diffusion model Cu-Sn diffusion couples [ 7 ].…”

Section: Introductionmentioning

confidence: 99%

Development and Characterization of Low Temperature Wafer-Level Vacuum Packaging Using Cu-Sn Bonding and Nanomultilayer Getter

et al. 2023

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Most microsensors are composed of devices and covers. Due to the complicated structure of the cover and various other requirements, it difficult to use wafer-level packaging with such microsensors. In particular, for monolithic microsensors combined with read-out ICs, the available process margins are further reduced due to the thermal and mechanical effects applied to IC wafers during the packaging process. This research proposes a low-temperature, wafer-level vacuum packaging technology based on Cu-Sn bonding and nano-multilayer getter materials for use with microbolometers. In Cu-Sn bonding, the Cu/Cu3Sn/Cu microstructure required to ensure reliability can be obtained by optimizing the bonding temperature, pressure, and time. The Zr-Ti-Ru based nanomultilayer getter coating inside the cap wafer with high step height has been improved by self-aligned shadow masking. The device pad, composed of bonded wafer, was opened by wafer grinding, and the thermoelectrical properties were evaluated at the wafer-level. The bonding strength and vacuum level were characterized by a shear test and thermoelectrical test using microbolometer test pixels. The vacuum level of the packaged samples showed very narrow distribution near 50 mTorr. This wafer-level packaging platform could be very useful for sensor development whereby high reliability and excellent mechanical/optical performance are both required. Due to its reliability and the low material cost and bonding temperature, this wafer-based packaging approach is suitable for commercial applications.

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“…Using the linear expansion method of Crack Tip Opening Displacement (CTOD), the relationship between geometric factors and crack length was determined, and a function equation to calculate the critical crack length of the fracture test was obtained. Wenchao Tian et al proposed a wafer-level, high-density microbump bonding technology and optimized the thickness, structure and layout of bonding materials by comparing and selecting good bonding processes [8][9][10]. Finally, they realized low-resistant electrical performance connections and obtained higher reliability, which is very useful for improving the reliability of 3D-system packaging.…”

Section: Introductionmentioning

confidence: 99%

Thermal Induced Interface Mechanical Response Analysis of SMT Lead-Free Solder Joint and Its Adaptive Optimization

et al. 2022

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Surface mount technology (SMT) plays an important role in integrated circuits, but due to thermal stress alternation caused by temperature cycling, it tends to have thermo-mechanical reliability problems. At the same time, considering the environmental and health problems of lead (Pb)-based solders, the electronics industry has turned to lead-free solders, such as ternary alloy Sn-3Ag-0.5Cu (SAC305). As lead-free solders exhibit visco-plastic mechanical properties significantly affected by temperature, their thermo-mechanical reliability has received considerable attention. In this study, the interface delamination of an SMT solder joint using a SAC305 alloy under temperature cycling has been analyzed by the nonlinear finite element method. The results indicate that the highest contact pressure at the four corners of the termination/solder horizontal interface means that delamination is most likely to occur, followed by the y-direction side region of the solder/land interface and the top arc region of the termination/solder vertical interface. It should be noted that in order to keep the shape of the solder joint in the finite element model consistent with the actual situation after the reflow process, a minimum energy-based morphology evolution method has been incorporated into the established finite element model. Eventually, an Improved Efficient Global Optimization (IEGO) method was used to optimize the geometry of the SMT solder joint in order to reduce the contact pressure at critical points and critical regions. The optimization result shows that the contact pressure at the critical points and at the critical regions decreases significantly, which also means that the probability of thermal-induced delamination decreases.

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Research of Wafer Level Bonding Process Based on Cu–Sn Eutectic

Cited by 13 publications

References 22 publications

Using Chiplet Encapsulation Technology to Achieve Processing-in-Memory Functions

Using Chiplet Encapsulation Technology to Achieve Processing-in-Memory Functions

Development and Characterization of Low Temperature Wafer-Level Vacuum Packaging Using Cu-Sn Bonding and Nanomultilayer Getter

Thermal Induced Interface Mechanical Response Analysis of SMT Lead-Free Solder Joint and Its Adaptive Optimization

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