ReSim: A reusable library for RTL simulation of dynamic partial reconfiguration

Abstract

Dynamic Partial Reconfiguration (DPR) enables software-like flexibility in hardware designs by allowing some of the logic on a Field Programmable Gate Array (FPGA) to be reconfigured while the rest continues to operate. However, such flexibility introduces challenges for verifying DPR design functionality because there is no straightforward way to simulate DPR at Register Transfer Level (RTL). This paper proposes the ReSim library to enable the RTL simulation of DPR. The library uses a simulation-only layer to hide the physically dependent details of DPR designs while providing sufficient accuracy for functional verification. The library is extensible and reusable. We assess the feasibility and demonstrate the value of our tool via two case studies of DPR designs.

RTL Simulation of High Performance Dynamic Reconfiguration: A Video Processing Case Study

“…ReSimbased simulation thereby captures the interaction between the user design and the FPGA fabric (e.g., the timing of reconfiguration events), and balances the need for accuracy with the requirement for physical independence [8]. However, mismatches between the simulation-only layer and the target FPGA can lead to bugs that would remain undetected by ReSim.…”

“…Unfortunately, simulating the bitstream traffic involves interpreting the bit-level configuration memory settings for the module to be configured, which undesirably exposes the details of the FPGA fabric to the verification of the user design. Our recent work, ReSim [8], [13], improves the simulation accuracy by using simulationonly bitstreams as substitutes for the real bitstreams so as to accurately model the transfer of bitstreams and the timing of reconfiguration, and is the first work to support the cycleaccurate RTL simulation of the complete reconfiguration process of an integrated DRS design. This paper presents a case study of applying ReSim to the verification of a real-world DRS design created using various IPs, and compares ReSim with the traditional MUX-based simulation approaches.…”

“…• An analysis of the challenges and opportunities for applying the IP-reuse design and verification methodology to DRS designs; and • An assessment of existing simulation approaches, Virtual Multiplexing [7] and ReSim-based simulation [8], in the functional verification of DRS designs.…”

Functionally verifying state saving and restoration in dynamically reconfigurable systems

“…By visualizing selected signals in a waveform viewer, RTL simulation assists in debugging a design without implementing it. In order to simulate partial reconfiguration of module logic, existing methods use multiplexers to interleave mutually exclusive modules [9], and use simulation-only bitstreams to capture the cycle-accurate behavior of module swapping [4]. This paper extends ReSim [4], our previous work, to support the simulation of a design reconfiguring both module logic and module state.…”

“…In order to simulate partial reconfiguration of module logic, existing methods use multiplexers to interleave mutually exclusive modules [9], and use simulation-only bitstreams to capture the cycle-accurate behavior of module swapping [4]. This paper extends ReSim [4], our previous work, to support the simulation of a design reconfiguring both module logic and module state. In particular, we consider designs that utilize the Configuration Port (CP) to save and restore state (e.g., [6] [11]).…”