Resistance switching for RRAM applications

Abstract

Resistive random access memory (RRAM or ReRAM) is a non-volatile memory (NVM) technology that consumes minimal energy while offering sub-nanosecond switching. In addition, the data stability against high temperature and cycling wear is very robust, allowing new NVM applications in a variety of markets (automotive, embedded, storage, RAM). Based on sudden conduction through oxide insulators, the characteristics of RRAM technology have still yet to be fully described. In this paper, we present our current understanding of this very promising technology.

Resistance instabilities in a filament-based resistive memory

“…10. The exponential voltage-time tradeoff [1,2] is also noted here. The continued RESET verification in the later stages of RESET must therefore avoid this turning point.…”

“…In turn, higher speed operation requires higher voltages, for both RESET and SET [1]. Even the initial voltage sweep for forming is applied over a much shorter duration and up to a higher voltage level than Figure 4.…”

“…Commonly, the resistance is located at localized conducting regions ("filaments") inside a metal oxide layer. Unlike phase-change memory (PCM) or magnetic random access memory (MRAM), where the resistance is programmed by current density thermally or magnetically inducing transitions over the entire electrically contacted region, typically, in an RRAM, ionized defects, such as oxygen vacancies or metal cations, are displaced by an electrical stress, resulting in the formation of filaments connecting the two electrodes or else subsequent disruption of the filaments [1,2]. Fig.…”

Electrical characterization and modeling of pulse-based forming techniques in RRAM arrays

“…The cell current I read was measured by applying V BL = 0.2 V, V WL = 1.4 V and a read time T read = 10 µs, t rise = t f all = 1µs. The Set/Reset operations were performed by using an Incremental Step Pulse algorithm [18,19], by increasing V BL from 1.5 V up to 3.5 V with ∆V BL = 0.1 V, V WL = 1.4 V and T pulse = 10 µs, t rise = t f all = 1µs during Set and by increasing the sourceline voltage V S L from 1.5 V up to 3.5 V with ∆V S L = 0.1 V, V WL = 2.8 V and T pulse = 10 µs, t rise = t f all = 1µs during Reset. Forming, Set, Reset and Read pulse operations are performed by applying the V S L , V BL and V WL cell-by-cell, sequentially.…”

Model of current-limited negative differential resistance in oxide-based resistance-switching devices

“…The SET process can be thought of as re-forming a filament after it had been previously ruptured by a RESET operation [5,6]. Since re-forming a filament does not need to generate oxygen vacancies in the entire oxide thickness, but only in the gap representing the filament portion that was ruptured (Fig.…”