Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives

Abstract

In‐memory computing is a computing scheme that integrates data storage and arithmetic computation functions. Resistive random access memory (RRAM) arrays with innovative peripheral circuitry provide the capability of performing vector‐matrix multiplication beyond the basic Boolean logic. With such a memory–computation duality, RRAM‐based in‐memory computing enables an efficient hardware solution for matrix‐multiplication‐dependent neural networks and related applications. Herein, the recent development of RRAM nanoscale devices and the parallel progress on circuit and microarchitecture layers are discussed. Well suited for analog synapse and neuron implementation, RRAM device properties and characteristics are emphasized herein. 3D‐stackable RRAM and on‐chip training are introduced in large‐scale integration. The circuit design and system organization of RRAM‐based in‐memory computing are essential to breaking the von Neumann bottleneck. These outcomes illuminate the way for the large‐scale implementation of ultra‐low‐power and dense neural network accelerators.

Automating Analogue AI Chip Design with Genetic Search

“…Several nonidealities cause the deterioration of the performance of memristive crossbar-based neural net architectures. Figure 1 shows some nonidealities such as a limited number of stable resistive states, [36][37][38] conductance variation, [39][40][41] memristor aging issues, [21] endurance, [34,42] reliability issues, [43] and device failure. [35] Limiting the number of stable resistive state leads to low precision of dot product multiplication, which, in turn, reduces the memristive neural network accuracy.…”

“…[44] The other type of memristor nonideality consists of nonlinear weight distribution, asymmetry and nonlinear programming, and device-to-device and cycle-to-cycle variation. [39,45,46] The hardware noise and R OFF /R ON ratio can also influence the design of the memristive neural network architectures. In addition, memristive crossbars are affected by sneak path currents, wire resistances, and leakage currents.…”

Integration and Co-design of Memristive Devices and Algorithms for Artificial Intelligence

“…These macro circuits can be tiled together according to the structure of deep neural networks to be constructed. For a more comprehensive review of peripherical circuits and large-scale integration, readers can refer to Yan et al, 2019 . These memristive DL accelerators are projected to be superior to CMOS-based or other solutions in several aspects, such as in performance (operation per second, OPS), area, and power efficiency ( Zhang et al., 2020a ; Sebastian et al., 2020 ).…”

“…TCAM can perform in-memory search and pattern matching between the query feature vector and stored vectors of binary bits. In the study by Yan et al, 2019a , Yan et al, 2019b , 2-transistor/2-RRAM TCAM cells were used to store the TCAM vectors. For each TCAM cell, the stored TCAM datum was defined as the bit “1” for RRAM1 in HRS and RRAM2 in LRS, the bit “0” for RRAM1 in LRS and RRAM2 in HRS, the bit “X” (do not care bit) for both RRAMs in HRS.…”

Recent Advancements in Emerging Neuromorphic Device Technologies

“…VMM operations are performed where the weights are physically stored, alleviating memory wall problems. [17] Therefore, for the in-memory computing platform based on the cross-point array architecture, [18] selecting the appropriate devices as the Figure 1. Transition to non von-Neumann architecture where the multiple synaptic array blocks for executing VMM in the place where the memories are stored in a similar manner are implemented, thereby eliminating memory wall bottleneck.…”