2018
DOI: 10.1109/ted.2017.2776085
|View full text |Cite
|
Sign up to set email alerts
|

Resistive Switching Device Technology Based on Silicon Oxide for Improved ON–OFF Ratio—Part II: Select Devices

Abstract: The cross-point architecture for memory arrays is widely considered as one of the most attractive solutions for storage and memory circuits thanks to simplicity, scalability, small cell size, and consequently high density and low cost. Cost-scalable vertical 3-D cross-point architectures, in particular, offer the opportunity to challenge Flash memory with comparable density and cost. To develop scalable cross-point arrays, however, select devices with sufficient ON-OFF ratio, current capability, and endurance … Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
4
1

Citation Types

1
37
0

Year Published

2019
2019
2023
2023

Publication Types

Select...
6

Relationship

3
3

Authors

Journals

citations
Cited by 67 publications
(38 citation statements)
references
References 27 publications
1
37
0
Order By: Relevance
“…Fig. 6(a) shows the measured and calculated switching voltages, namely, V T+ , V H+ , V T− and V H− , as a function of I C [27]. The calculation results agree with the experimental data in the broad range from 0.1 to 80 μA.…”
Section: Simulation Resultssupporting
confidence: 67%
See 2 more Smart Citations
“…Fig. 6(a) shows the measured and calculated switching voltages, namely, V T+ , V H+ , V T− and V H− , as a function of I C [27]. The calculation results agree with the experimental data in the broad range from 0.1 to 80 μA.…”
Section: Simulation Resultssupporting
confidence: 67%
“…DC Characteristics Fig. 5(a) shows the structure of the volatile RRAM with Ag/SiO x /C stack and a select transistor to control the maximum current, namely I C [27]. The thickness of the dielectric layer was L = 5nm.…”
Section: Simulation Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…For the (Pt/HfO 2 /W) Set (cycle in Figure a), a positive voltage of 2.8 V is required, while for the Reset operation, the memory switches from LRS to HRS showing two intermediate steps at −0.9 and −1.5 V with a high overshoot current. Reset current overshoot is caused due to the large value of the V Set that makes the fast current rising (in range of few μs) before the current limiting tool can overcome the voltage drop across the circuits . Moreover, this device tends to show high current fluctuation through the Set operation before the abrupt Set occurs.…”
Section: Resultsmentioning
confidence: 99%
“…The stochastic behavior of t D is a consequence of the ion migration in RRAM being dependent on the local microstructure and atomistic migration of ions. [132] In this type of devices, the Ag migration from the TE results in the formation of an unstable CF, which decays soon after the set transition with a retention time ranging from few µs to few ms. [133][134][135][136] The volatile behavior is the result of the large diffusivity of Ag combined with the mechanical compressive stress in the dielectric layer [137] and the tendency to minimize the surface to volume ratio of the CF. This can be explained by the set transition being a thermally activated process to overcome an energy barrier E A which controls the time constant according to the Arrhenius law τ = τ 0 exp (E A /kT), where τ 0 is a constant, k is the Boltzmann constant, and T is the local temperature.…”
Section: Stochastic Delay Timementioning
confidence: 99%