Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Abstract

With the continuous scaling of CMOS technology, integrating an embedded high-density non-volatile memory appears to be more and more costly and technologically challenging. Beyond floating-gate memory technologies, bipolar Resistive Random Access Memories (RRAM) appear to be one of the most promising technologies. However, when organized in a 1 or 2-Transistor 1-RRAM (1T1R, 2T1R) architectures, they suffer from large bitcell area, degraded performance and reliability issue during reset operation. The association of multiple-independentgate Polarity Controllable Transistors (PCT) with RRAM overcomes these drawbacks, while providing a dense structure. In this paper, we present two innovative PCT-based bitcells and propose an extensive study of their functionality, physical design considerations and performances in read and write operations compared to CMOS-based 1T1R and 2T1R bitcells. The proposed bitcells outperform the performances of 1T1R and 2T1R bitcells in reset (5× to 105× speed improvement) are competitive in term of area (1.35× to 2.6× area reduction versus 2T1R) and avoid gate overdrive (1.2V versus more than 2V in 1T1R bitcells) thus reducing selector reliability concerns. We also propose an innovative programming strategy which takes advantage of the PCT polarity control and enabling 500× improvement in reset performance. Finally, the proposed bitcells performs 15 to 67% faster than CMOS bitcells in read.

Functionality Enhanced Memories for Edge-AI Embedded Systems

“…In [8], we explored the opportunities opened by polarity control to design 1Transistor-1RRAM bitcell enabling low voltage reset operation in the context of 2-terminal bipolar RRAM technologies (i.e., filamentary RRAM or STT-MRAM). In [8], both polarity gates were connected together, enabling the transistor to be configured in n-type during a set operation and p-type during a reset operation, thereby enabling a gate-overdrive-free reset operation. In this work, we propose to couple the polarity control with breakthrough array organization schemes.…”

“…Thanks to their three gates, a polarity control can be enabled as introduced section II-B. In that sense, we propose here to use the mechanism demonstrated in [8] to perform bidirectional read operations. horizontal real operations are performed by setting up the TIGFET in n-type, and vertical accesses are performed by setting up the TIGFETs in p-type.…”

“…This new functionality is enabled by the independent use of TIGFET's polarity gates and can be used to enable (i) direct (LSB/MSB) comparisons or (ii) transposed access in the case of 1 word per bitcell (i.e., binarized data or Multiple Level Cells, MLC, RRAM). Finally, SiNWFET-based RRAM array enable strong energy gains [8] and we propose to explore macrolevel consideration regarding sense and write amplifiers overhead.…”