Resource-aware run-time elaboration of behavioural FPGA specifications

Abstract

The Circal process algebra is being used to explore the behavioural specification of systems that are mapped to field programmable logic circuits. In this paper we report on the implementation and performance of an interpreter for system specifications given in the Circal language. In contrast to the typical design flow for field programmable technology in which designs are statically partitioned, synthesised, and mapped to pre-allocated resources, in this system the specified circuits are extracted from behavioural specifications that are partitioned, elaborated, mapped, and configured at run time as control passes through them. We report on the details of a design that targets the Celoxica RC1000 co-processor and assess preliminary performance results for this implementation. The results clearly demonstrate our method is a practical approach to overcome resource constraints, particularly in applications where these change at run time. The results also establish a benchmark against which to measure future improvements and alternative methods.

Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores

“…Research on reconfigurable architectures covers a broad spectrum of topics such as System-on-Chip [2], run-time reconfiguration techniques [9], interconnection networks [8], and even fundamental floating-point operations like division and square root [5,6]. The increased gate count, arithmetic capability, and other features of modern FPGAs [1,13] now allow researchers to investigate general-purpose floating-point computational kernels such as linear algebra routines [12] or iterative solvers [4], and computational kernels from specific problem domains such as molecular dynamics [10].…”