Resource constrained dataflow retiming heuristics for VLIW ASIPs

“…A Hardware/Software partitioning algorithm for automatic synthesis of a pipelined ASIP with multiple identical functional units with area constraints is introduced in [5]. The code generation for time critical loops for Very Large Instruction Word (VLIW) ASIPs with heterogenous distributed register structure is addressed in [11]. In [12] a methodology for early space exploration of VLIW ASIPs with a clustered datapath is proposed.…”

Section: Related Workmentioning

confidence: 99%

Dual-pipeline heterogeneous ASIP design

Radhakrishnan

Guo

Parameswaran

2004

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS

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In this paper we demonstrate the feasibility of a dual pipeline Application Specific Instruction Set Processor. We take a C program and create a target instruction set by compiling to a basic instruction set, from which some instructions are merged, while others discarded. Based on the target instruction set, parallelism of the application program is analyzed and two unique instruction sets are generated for a heterogeneous dual-pipeline processor. The dual pipe processor is created by making two unique ASIPs (VHDL descriptions) utilizing the ASIP-Meister Tool Suite, and fusing the two VHDL descriptions to construct a dual pipeline processor. Our results show that in comparison to the single pipeline Application Specific Instruction Set Processor, the performance improves by 27.6% and switching activity reduces by 6.1% for a number of benchmarks. These improvements come at the cost of increased area which for benchmarks considered is 16.7% on average.

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“…Leiserson et al first established the theoretical foundation for retiming synchronous circuits [42], and this has been extended to loop scheduling for VLIW processors [56,15,35]. Shifting tasks in a data flow graph (DFG) across the iteration boundary can result in a shorter execution time or alleviate the resource pressure (e.g.…”

Section: Related Workmentioning

confidence: 99%

Integrated Management of Power Aware Computation and Communication (IMPACCT)

Chou¹,

Bagherzadeh²

2003

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Resource constrained dataflow retiming heuristics for VLIW ASIPs

Cited by 10 publications

References 10 publications

Customization of application specific heterogeneous multi-pipeline processors

Customization of application specific heterogeneous multi-pipeline processors

Dual-pipeline heterogeneous ASIP design

Integrated Management of Power Aware Computation and Communication (IMPACCT)

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