Resource Management for Mixed-Criticality Systems on Multi-core Platforms with Focus on Communication

2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)

2020

This paper presents a new ASIC design of a coprocessor that performs process scheduling for embedded mixed-criticality real-time systems consisting of processes of various criticality and various real-time attributes. The proposed solution is implementing Robust Earliest Deadline (RED) algorithm and previously developed hardware architectures used for scheduling of real-time processes. Thanks to the on-chip implementation of the scheduler in a form of a coprocessor, the scheduler operations can be completed in two clock cycles regardless of the process amount within the system contains. The proposed scheduler was verified by simulations that applied millions of random inputs. Chip area costs are evaluated by synthesis into an ASIC using 28 nm process by TSMC. Two versions of real-time process schedulers were compared: EDF scheduler designed for hard real-time processes only and the proposed RED scheduler. The RED algorithm handles variations of process execution times better, achieves higher CPU utilization and can be used for scheduling of hard real-time, soft real-time and non-real-time processes combined within one system that is not possible using the other scheduling algorithms.

Section: Future Improvementsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

ASIC Architecture and Implementation of RED Scheduler for Mixed-Criticality Real-Time Systems

2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)

2020

“…Since in mixed-criticality real-time embedded systems various task types can co-exist within one system, the need for a robust task scheduler arises to support all types of tasks. [5][6][7] Therefore, we decided to develop a novel real-time task scheduling coprocessor based on RED algorithm such that it is suitable also for soft realtime tasks. [1][2][3][4] We propose a solution in the form of a coprocessor unit that implements the RED-based scheduling algorithm.…”

Section: Proposed Solutionmentioning

confidence: 99%

“…Since the average execution time is usually much shorter than WCET, resources had to be reserved much longer than what was actually needed in most cases for the execution of safetycritical tasks. [5][6][7][8] It is nowadays acknowledged that safety-critical applications should be able to run on the same platform as noncritical applications, complete isolation being deemed too costly with the spread of systems-on-chip. This is regarded as a way to improve resource utilization, by running low or noncritical tasks on slack time made available when a high-critical task terminates before its WCET, which is very common in practice.…”

Section: Introductionmentioning

confidence: 99%

A Novel On-Chip Task Scheduler for Mixed-Criticality Real-Time Systems

Nagy

2019

J CIRCUIT SYST COMP

This paper presents a novel design of a coprocessor that performs hardware-accelerated task scheduling for embedded real-time systems consisting of mixed-criticality real-time tasks. The proposed solution is based on the Robust Earliest Deadline (RED) algorithm and previously developed hardware architectures used for scheduling of real-time tasks. Thanks to the HW implementation of the scheduler in the form of a coprocessor, the scheduler operations (i.e., instructions) are always completed in two clock cycles regardless of the actual or even maximum task amount within the system. The proposed scheduler was verified using simplified version of UVM and applying billions of randomly generated instructions as inputs to the scheduler. Chip area costs are evaluated by synthesis for Intel FPGA Cyclone V and for 28-nm TSMC ASIC. Three versions of real-time task schedulers were compared: EDF-based scheduler designed for hard real-time tasks only, GED-based scheduler and the proposed RED-based scheduler, which is suitable for tasks of various criticalities. According to the synthesis results, the RED-based scheduler consumes LUTs and occupies larger chip area than the original EDF-based scheduler with equivalent parameters used. However, the RED-based scheduler handles variations of task execution times better, achieves higher CPU utilization and can be used for the scheduling of hard real-time, soft real-time and nonreal-time tasks combined in one system, which is not possible with the former algorithms.

“…However, process isolation forces systems to be under-utilized and to use pessimistic analysis of worst-case execution time for each process. On the other hand, average execution time is usually significantly smaller than the worstcase time [1][2][3].…”

Section: Introductionmentioning

confidence: 99%

RED-based Scheduler on Chip for Mixed-Criticality Real-Time Systems

Nagy

2020 9th Mediterranean Conference on Embedded Computing (MECO)

2020

Real-time embedded systems that combine processes of various criticalities (i.e. mixed-criticality real-time systems) represent an emerging research that faces many issues. This paper describes a new ASIC design of a coprocessor that realizes process scheduling for mixed-criticality real-time systems. The solution proposed in this paper uses Robust Earliest Deadline (RED) algorithm. Due to the on-chip implementation of the scheduler, all scheduler operations always take two clock cycles to execute. The proposed solution was verified by simulations that applied millions of random inputs. Chip area costs are evaluated by synthesis into ASIC using 28 nm TSMC technology. The proposed RED-based scheduler is compared with an existing EDF-based scheduler that supports hard realtime processes only. Even though the RED-based scheduler costs more chip area, it can handle any combinations of process criticalities, variations of process execution times and deadlines, achieves higher CPU utilization and can be used for scheduling of non-real-time, soft real-time and hard real-time processes combined within one system.