Resource Optimal Truncated Multipliers for FPGAs

Böttcher, Andreas; Kumm, Martin; Dinechin, Florent de

doi:10.1109/arith51176.2021.00029

Cited by 9 publications

(5 citation statements)

References 24 publications

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“…It calculates the number of bits to shift based on the mantissa sizes (line 8) and performs a right shift, either rounding or truncating the mantissa based on whether EN_ROUNDING is defined (lines 9-13). Next, the function adjusts the exponent by adding the exponents of x and y along with any overflow bits detected from the normalization process (lines [16][17]. It determines the sign of the result by XORing the signs of the operands (line 20).…”

Section: Primary Operationsmentioning

confidence: 99%

“…It aligns all mantissas to this maximum exponent by computing exponent differences and shifting the mantissas accordingly (lines [13][14]. After applying the signs to the mantissas, they are summed using a recursive template adder, and the resulting sign is determined (lines [17][18][19]. The rest is quite similar to the sum operation elaborated in the previous subsection.…”

Section: Vector Summationmentioning

confidence: 99%

“…One of the works at the RTL level is proposed in [13], where floating-point operator entities receive general inputs that define floating-point types, and the data-path widths are established during the elaboration phase. Flopoco [14] stands out as a significant research effort at the RTL level and serves as a foundation for numerous other researches [15][16][17][18].…”

Section: Introductionmentioning

confidence: 99%

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CuFP: An HLS Library for Customized Floating-Point Operators

Hajizadeh,

Ould-Bachir,

David

2024

Preprint

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High-Level Synthesis (HLS) tools have revolutionized FPGA application development by providing a more efficient and streamlined approach, significantly impacting digital design methodologies. Despite the capability of FPGAs to customize numerical representations in data paths, most HLS projects have focused on fixed-point precision, while floating-point representations remain limited to vendor-provided single, double, and half-precision formats. This paper proposes a customized floating-point library compatible with HLS to address these limitations. This library allows programmers to define the number of exponent and mantissa bits at compile time, providing greater flexibility and enabling the use of mixed precision. Moreover, this library includes optimized implementations of common components such as vector summation (VSUM), dot-product (DP), and matrix-vector multiplication (MVM). Results demonstrate that the proposed library reduces latency and resource utilization compared to vendor IP blocks, particularly in VSUM, DP, and MVM operations. For example, the MVM operation involving a 32x32 matrix, using vendor IP requires 22 clock cycles, whereas CuFP completes the same task in just 7 clock cycles, using approximately 60% fewer DSPs, 10% fewer LUTs, and 60% fewer FFs.

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Section: Primary Operationsmentioning

confidence: 99%

Section: Vector Summationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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CuFP: An HLS Library for Customized Floating-Point Operators

Hajizadeh,

Ould-Bachir,

David

2024

Preprint

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“…Hence, the tiling problem is defined as finding a valid tiling with minimal cost for a given set of tiles (i.e., sub-multipliers). Various heuristic [17]- [19] and optimal [20], [21] methods have been proposed to solve the tiling problem and to trade between DSP and complementary LUT-resources.…”

Section: Multiplier Tiling a Basic Ideamentioning

confidence: 99%

“…O x,y is another set of binary constants that describes the shape of the overall multiplier. O x,y is usually set to one for all valid positions but can be set to zero for the least significant bits in truncated multipliers [16], [21].…”

Section: Previous Multiplier Tiling Ilp Modelmentioning

confidence: 99%

Resource Optimal Squarers for FPGAs

Böttcher

Kumm

Dinechin

2022

2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)

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Squaring is an essential operation in computer arithmetic that can be considered as a special case of multiplication where several simplifications can be applied to reduce the complexity of the resulting circuit. However, the design of a squarer is not straightforward for modern FPGAs that provide embedded DSP blocks and look-up-tables (LUTs). This work proposes a flexible method to design resource optimal squarers, i.e., a squarer that uses a minimum number of LUTs for a userdefined number of DSP blocks. The method uses an integer linear programming (ILP) formulation based on a generalization of multiplier tiling. It is shown that the proposed squarer design method significantly improves the LUT utilization for a given number of DSPs over previous methods, while maintaining a similar critical path delay and latency.

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Fixed-Point Multiplication

de Dinechin,

Kumm

2023

Application-Specific Arithmetic

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Resource Optimal Truncated Multipliers for FPGAs

Cited by 9 publications

References 24 publications

CuFP: An HLS Library for Customized Floating-Point Operators

CuFP: An HLS Library for Customized Floating-Point Operators

Resource Optimal Squarers for FPGAs

Fixed-Point Multiplication

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