Response surface modeling for parasitic extraction for multi-objective optimization of multi-chip power modules (MCPMs)

Le, Quang Trung; Evans, Tristan M.; Mukherjee, Shilpi; Peng, Yarui; Vrotsos, Tom; Mantooth, H. Alan

doi:10.1109/wipda.2017.8170568

Cited by 11 publications

(2 citation statements)

References 21 publications

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“…5(b). The response surface model described in [17] is then used to evaluate the self-parasitic values of every edge. The mutual inductance between every two edges can be evaluated using equations in [11].…”

Section: Methodsmentioning

confidence: 99%

PowerSynth progression on layout optimization for reliability and signal integrity

Peng

Razi

et al. 2020

NOLTA

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PowerSynth has been developed to significantly accelerate power module design through a multi-objective layout synthesis and optimization process. It uses a series of layout generation and optimization algorithms and various electrical and thermal models to automatically synthesize power module layouts and create a Pareto surface of solutions with optimum electrical and thermal performance. Recent advanced power modules are designed with various types of components integrated on multiple device layers to minimize the parasitics and increase power density. With more compact layouts and tighter design constraints, power module design becomes increasingly challenging because of reliability and signal integrity issues, such as partial discharge, electromagnetic interference (EMI), electro migration, and noise-induced false turn-on. This paper summarizes the latest PowerSynth layout engine and model improvements with an emphasis on the new reliability and signal integrity features. A generic and scalable constraint-aware layout engine is developed to process generic types of devices, traces, and connectors in power modules. Electrical models are improved from a 1D wire model to a 2D mesh model with enhanced feature sets to better capture the intrinsic layout structures and extract coupling between power and gate loops. EMI models are built on top of it to further reduce the noise analysis and qualification requirement posted on designers. Finally, a new post-layout optimization step is included in the flow as an improvement of design for manufacturability and reliability. The software development along with the hardware testing results demonstrates the latest advances in design automation for power electronics.

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Section: Methodsmentioning

confidence: 99%

PowerSynth progression on layout optimization for reliability and signal integrity

Peng

Razi

et al. 2020

NOLTA

Self Cite

View full text Add to dashboard Cite

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“…However, the above-mentioned methods tend to be computationally costly when multiple consecutive inductance extractions are to be performed, what limits their usability for layout optimization. For optimization where the computational time of the parasitic inductance extraction is a crucial factor, more commonly used methods are to utilize lumped element circuit methodologies, such as with analytical microstrip equations available in PowerSynth [1] with some accuracy loss, or crude mesh analysis present in FastHenry [2]. Recent developments brought FFT-accelerated partial element equivalent circuit (PEEC) [3] and volume integral equation (VIE) [4] methods, achieving a significant reduction in computation time while maintaining good accuracy.…”

Section: Introductionmentioning

confidence: 99%

Ultra-Fast Power Module Inductance Estimation using Convolutional Neural Networks

Kubulus,

Michal Beczkowski,

Munk-Nielsen

et al. 2023

2023 IEEE Energy Conversion Congress and Exposition (ECCE)

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The widespread usage of wide bandgap (WBG) semiconductors forces extra emphasis on the early estimation of the layout parasitic elements. Be it a printed circuit board or a power module, layout optimization is necessary to minimize the negative effects of present inductances. Unfortunately, multiple invocations of inductance extraction software can be timeconsuming. In this work, state-of-the-art convolutional neural networks (CNN) are applied in order to lower the time consumption of inductance estimation without compromising the accuracy.

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Hierarchical Layout Synthesis and Design Automation for 2.5D Heterogeneous Multi-Chip Power Modules

Razi

Mantooth

et al. 2019

2019 IEEE Energy Conversion Congress and Exposition (ECCE)

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Response surface modeling for parasitic extraction for multi-objective optimization of multi-chip power modules (MCPMs)

Cited by 11 publications

References 21 publications

PowerSynth progression on layout optimization for reliability and signal integrity

PowerSynth progression on layout optimization for reliability and signal integrity

Ultra-Fast Power Module Inductance Estimation using Convolutional Neural Networks

Hierarchical Layout Synthesis and Design Automation for 2.5D Heterogeneous Multi-Chip Power Modules

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