Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor

Rihani, Hamza; Moy, Matthieu; Maïza, Claire; Davis, Robert I.; Altmeyer, Sebastian

doi:10.1145/2997465.2997472

Cited by 39 publications

(57 citation statements)

References 24 publications

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“…Examples include: (i) covering processor clusters and multi-level bus/network-on-chip (NoC) arbitration policies. Initial work in this area is reported in (Rihani et al 2016). (ii) covering processor scheduling policies where analysis of cache-related pre-emption delays already exists, such as fixed-priority scheduling with pre-emption thresholds (Bril et al 2014(Bril et al , 2017, and EDF (Lunniss et al 2013).…”

Section: Discussionmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

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In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on contextindependent WCET values. Instead, the analysis formulates response times directly The additional material includes: Section 4: analysis for warmed-up caches and dynamic scratchpads (Sects. 4.3 and 4.2). Section 7: extensions to the task model, including RTOS and interrupts, shared software resources, and open systems and incremental verification. Section 8: presentation of a cycle-accurate multicore simulator. Section 9: evaluation of different local memory types (Sect. 9.2), a comparison between predictable and reference architectures (Sect. 9.3), and a verification of the precision of the analysis using results from the simulator (Sect. 9.4). 123Real-Time Syst from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.

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Section: Discussionmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

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“…To tackle with over-approximated WCETs due to interferences, several approaches incorporate interference analysis and provide interference-sensitive WCETs, e.g. [19], [20], [4], [5], [6]. In general, these approaches result in improved timing guarantees, compared to over-approximated WCETs, as they provide a context-dependent upper-bound of the interferences for a particular schedule.…”

Section: Related Workmentioning

confidence: 99%

“…To improve the provided upper-bounds, some approaches take into account the length of task overlapping, e.g. [5], or the precise timing of the requests, e.g. [21], or even provide contention-free schedules, e.g.…”

Section: Related Workmentioning

confidence: 99%

“…In the first case, the pessimism introduced in the WCET estimation (by being unaware of the task scheduling and allocation solution) can potentially negate the performance benefit coming from the parallel execution of the tasks on multi-cores [1] or even make the problem infeasible, if the system becomes unschedulable. In the second case, the known task scheduling and allocation solution is used to compute interference-sensitive WCET (isWCET), which are lower than the pessimistic WCET of the first case [3], [4], [5].…”

Section: Introduction a Contextmentioning

confidence: 99%

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Timely Fine-Grained Interference-Sensitive Run-Time Adaptation of Time-Triggered Schedules

Skalistis

Kritikakou

2019

2019 IEEE Real-Time Systems Symposium (RTSS)

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In time-critical systems, run-time adaptation is required to improve the performance of time-triggered execution, derived based on Worst-Case Execution Time (WCET) of tasks. By improving performance, the systems can provide higher Quality-of-Service, in safety-critical systems, or execute other best-effort applications, in mixed-critical systems. To achieve this goal, we propose a parallel interference-sensitive run-time adaptation mechanism that enables a fine-grained synchronisation among cores. Since the run-time adaptation of offline solutions can potentially violate the timing guarantees, we present the Response-Time Analysis (RTA) of the proposed mechanism showing that the system execution is free of timing-anomalies. The RTA takes into account the timing behavior of the proposed mechanism and its associated WCET. To support our contribution, we evaluate the behavior and the scalability of the proposed approach for different application types and execution configurations on the 8-core Texas Instruments TMS320C6678 platform. The obtained results show significant performance improvement compared to state-of-the-art centralized approaches.

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“…The off-line computation with a constraint programming approach is also classic as for instance done in [38,23,5,11]. In [42], the authors propose an off-line mapping of Scade/lustre programs on the Kalray MPPA to improve the WCET. In the continuation of the former work, Graillat and al.…”

Section: Predictable Executionmentioning

confidence: 99%

Automated generation of time-predictable executables on multicore

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et al. 2018

Proceedings of the 26th International Conference on Real-Time Networks and Systems

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In this paper, we are interested in the implementation of control-command applications, such as the flight control system of an aircraft for instance, on multi-core hardware. Due to certification and safety issues, time-predictability-in the sense that the timing behavior must be analysable and validable off-line-is a mandatory feature. We present a complete framework, from high-level system specification in synchronous languages, to implementation on a multi-core hardware platform, which enforces time-predictability at every step of the development process. The framework is based on automated code generation tools to speed-up the development process and to eliminate error-prone human-made translation steps.

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Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor

Cited by 39 publications

References 24 publications

An extensible framework for multicore response time analysis

An extensible framework for multicore response time analysis

Timely Fine-Grained Interference-Sensitive Run-Time Adaptation of Time-Triggered Schedules

Automated generation of time-predictable executables on multicore

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