ReStore: Symptom-Based Soft Error Detection in Microprocessors

Wang, N.J.; Patel, Sanjay J.

doi:10.1109/tdsc.2006.40

Cited by 192 publications

(139 citation statements)

References 27 publications

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“…The saturation of fault coverage provided by symptom based methods is expected because these schemes rely on rare hardware exceptions such as page faults, divide-by-zero, etc. If more frequently occurring microarchitectural events such as branch mispredicts and cache misses are included as symptoms, then recovery may be triggered more frequently, leading to an unacceptable amount of overhead [32]. In general, symptom-based methods provide good coverage at a relatively low overhead.…”

Section: Proposed Solution Landscapementioning

confidence: 99%

“…Wang and Patel [32] indicate that checkpointing and recovery are possible if the fault can be detected within a window of 1000 instructions for speculated pipelines. The results presented in Section 5 assume that in modern/future processors, a mechanism for recovering to a checkpointed state of 1000 instructions in the past will already be required for aggressive performance speculation.…”

Section: Recovery Supportmentioning

confidence: 99%

“…A light-weight approach for detecting soft errors, ReStore [32], analyzes symptoms including memory exceptions, branch mispredicts, and cache misses. In our proposed solution, extra symptom generating instructions are introduced based on value-profiling data.…”

Section: Related Workmentioning

confidence: 99%

“…This work is built upon two areas of prior research: symptom-based fault detection and software-based instruction duplication. Symptom-based detection schemes recognize that applications often exhibit anomalous behavior (symptoms) in the presence of a transient fault [17,32]. These symptoms can include memory access exceptions, divide-by-zero, and even mispredicted branches.…”

Section: Introductionmentioning

confidence: 99%

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Efficient soft error protection for commodity embedded microprocessors using profile information

Khudia

Wright

Mahlke

2012

Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Syst

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Successive generations of processors use smaller transistors in the quest to make more powerful computing systems. It has been previously studied that smaller transistors make processors more susceptible to soft errors (transient faults caused by high energy particle strikes). Such errors can result in unexpected behavior and incorrect results. With smaller and cheaper transistors becoming pervasive in mainstream computing, it is necessary to protect these devices against soft errors; an increasing rate of faults necessitates the protection of applications running on commodity processors against soft errors. The existing methods of protecting against such faults generally have high area or performance overheads and thus are not directly applicable in the embedded design space. In order to protect against soft errors, the detection of these errors is a necessary first step so that a recovery can be triggered.To solve the problem of detecting soft errors cheaply, we propose a profiling-based software-only application analysis and transformation solution. The goal is to develop a low cost solution which can be deployed for off-the-shelf embedded processors. The solution works by intelligently duplicating instructions that are likely to affect the program output, and comparing results between original and duplicated instructions. The intelligence of our solution is garnered through the use of control flow, memory dependence, and value profiling to understand and exploit the common-case behavior of applications. Our solution is able to achieve 92% fault coverage with a 20% instruction overhead. This represents a 41% lower performance overhead than the best prior approaches with approximately the same fault coverage.

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Section: Proposed Solution Landscapementioning

confidence: 99%

Section: Recovery Supportmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Efficient soft error protection for commodity embedded microprocessors using profile information

Khudia

Wright

Mahlke

2012

Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Syst

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“…Software techniques for error detection and correction include redundant execution, which is redundancy in time, to ensure reliability against soft errors [17,13,78,79,80]. In general, this approach creates multiple copies of the same execution to detect any mismatch in the application output, and consequently chooses the right output to ensure reliable execution.…”

Section: Software Techniquesmentioning

confidence: 99%

ReSense: A Unified Framework for Improving Performance and Reliability in Multicore Architectures

Dey

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Chip-multiprocessors (CMPs) have become ubiquitous in modern computing and the mainstream architecture for various platforms, including laptops, desktops, and large server machines. As technology scaling continues and more transistors are accommodated on the chip, the number of cores on CMPs is growing, and multi-core machines are scaling up to many-core machines. With this multi-core scaling, two major problems arise: shared-resource contention and soft errors or transient faults. Shared-resource contention can degrade an application's performance significantly, and soft errors increase the probability of incorrect application execution and the production of visible errors. To realize the full potential of multi-and many-core platforms, it is critical to ensure that applications in a workload not only execute e ciently and fast, but also correctly.In this dissertation, we develop a novel, general, and unified framework, ReSense, to address several challenges on multicore architectures including performance optimization, reliability improvement, power and thermal management. The framework includes five components: a general characterization methodology, a characterization metric, a sensitivity score, a thread mapping algorithm, and a run-time system. An instance of the framework is applied in two phases: characterization and mapping. The characterization phase utilizes the general characterization methodology and characterization metric to identify application characteristics without considering any co-runner(s). It generates a resource-sensitivity score for each application in a workload. In the mapping phase, the run-time system uses a thread-mapping algorithm and the sensitivity scores of the applications in a workload to c Abstract d determine the thread-mappings that optimize the objective function of the targeted problem.To demonstrate the utility and e ectiveness of ReSense, we use it to address the problems of shared-resource contention and soft errors for multi-threaded applications. For the resource contention problem, the characterization methodology determines how a multi-threaded application's performance is a ected as it shares a resource in the memory hierarchy. A sensitivity score based on resource contention is produced for each application in a workload.The run-time system uses the resource-contention sensitivity scores and a thread-mapping algorithm to allocate threads from a workload to core to mitigate shared-resource contention, thus improving response time and throughput.For the soft error problem, the characterization methodology determines how a multithreaded application's vulnerability to soft errors in shared caches is a ected by its resource occupancy duration. A sensitivity score based on cache occupancy is produced for each application in a workload. The run-time system uses the cache-occupancy sensitivity scores and a thread-mapping algorithm to allocate workload threads to cores to reduce the occupancy in the shared caches, thus reducing cache vulnerability.Both minimizing...

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Processor Level Error Detection and Recovery

2024

Dependable Computing

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ReStore: Symptom-Based Soft Error Detection in Microprocessors

Cited by 192 publications

References 27 publications

Efficient soft error protection for commodity embedded microprocessors using profile information

Efficient soft error protection for commodity embedded microprocessors using profile information

ReSense: A Unified Framework for Improving Performance and Reliability in Multicore Architectures

Processor Level Error Detection and Recovery

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