Results From the ColdFlux Superconductor Integrated Circuit Design Tool Project

Fourie, Coenrad J.; Jackman, Kyle; Delport, Johannes; Schindler, Lieze; Hall, Tessa; Febvre, Pascal; Iwanikow, Lucas; Chen, Olivia; Ayala, Christopher L.; Yoshikawa, Nobuyuki; Law, Mark; Weingartner, Thomas A.; Wang, Yanzhi; Beerel, Peter; Gupta, Sandeep; Zha, Haipeng; Razmkhah, Sasan; Karamuftuoglu, Mustafa Altay; Fayyazi, Arash; Li, Mingye; Annavaram, Murali; Nazarian, Shahin; Pedram, Massoud

doi:10.1109/tasc.2023.3306381

Cited by 7 publications

(3 citation statements)

References 125 publications

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“…This work introduces a collection of new superconductive logic cells inspired by the cells demonstrated in [12,31] designed to achieve compact layouts. This logic family leverages high critical current density (J C ) 0 and π Josephson Junctions (JJs) to establish an ALL-JJ-based superconductive logic cell family, named fast phase logic (FPL).…”

Section: Fast Phase Logic (Fpl)mentioning

confidence: 99%

“…Despite the numerous merits of RSFQ circuits, they are not free of substantial challenges. Notably, the integration density of RSFQ circuits remains relatively modest, with MIT Lincoln Laboratory achieving less than 1 Million JJ per chip to increase it to 4 million JJs [11], which is in the orders of 10,000 logic gates accommodating a chip area of 1 cm 2 based on synthesis and area estimation results in [12]. This scale of integration is inadequate to meet the computational requirements posed by today's demanding applications.…”

Section: Introductionmentioning

confidence: 99%

“…FPL is presented in this work. The HFQ cells are from[31], and RSFQ cells were developed during the ColdFlux project[12].…”

mentioning

confidence: 99%

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High-density superconductive logic circuits utilizing 0 and π josephson junctions

Razmkhah,

Pedram

2024

Eng. Res. Express

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Superconductor Electronics (SCE) is a fast and power-efficient technology with great potential for overcoming conventional CMOS electronics' scaling limits. Nevertheless, the primary challenge confronting SCE today is its integration level, which lags several orders of magnitude behind CMOS circuits. In this study, we have innovated and simulated a novel logic family grounded in the principles of phase shifts occurring in 0 and π Josephson junctions. The fast phase logic (FPL) eliminates the need for large inductor loops and shunt resistances by combining the half-flux and phase logic. Therefore, the Josephson junction (JJ) area only limits the integration density. The cells designed with this paradigm are fast, and the clock-to-Q delay for logic cells is about 4ps. While maintaining over 50% parameter margins for wiring cells. This logic is power efficient and can increase the integration by at least 100 times in the SCE chips.

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Section: Fast Phase Logic (Fpl)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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High-density superconductive logic circuits utilizing 0 and π josephson junctions

Razmkhah,

Pedram

2024

Eng. Res. Express

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An Integrated Approach towards VLSI Implementation of SFQ Logic using Standard Cell Library and Commercial Tool Suite

Meher,

Eren Çelik,

Ravi

et al. 2024

J. Phys.: Conf. Ser.

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The semiconductor industry seeks energy-efficient alternatives as Moore’s law nears its limits. The Single Flux Quantum (SFQ) integrated circuits (ICs) using thousands of niobium Josephson junctions (JJs) and operating at 4 K show great promise for digital computing circuits at high speed (>20 GHz) and low power (a few nW per junction). The leading logic families are Rapid Single Flux Quantum (RSFQ), and its energy-efficient variant (ERSFQ). IARPA’s SuperTools program aims to develop integrated design tools for superconductor electronics, targeting SFQ and Adiabatic Quantum-Flux-Parametron (AQFP) logic families. This paper presents a passive transmission line (PTL) based standard cell library for SFQ logic, designed with Synopsys Electronic Design Automation (EDA) software tools for MIT-LL 100μA/μm2 SFQ5ee fab node. The dual RSFQ/ERSFQ standard cell library facilitates seamless integration of SFQ RTL-to-GDS design flow with Synopsys Fusion Compiler, an automated design tool. The SFQ RTL-to-GDS flow entails logic synthesis, checking, placement, clock synthesis, and routing. Row-based placement for library cells and H-tree clock tree structures are employed. Fusion Compiler’s effectiveness is validated with Hypres designs such as finite impulse response (FIR) filters, scalable multiply-accumulate (MAC) units, and memory arrays, comparing single and dual clocking schemes. The synergy between Hypres and Synopsys achieves a milestone by demonstrating the design of a digital superconducting circuit with over 10 million JJs, facilitated by a fully automated design tool for the first time. Challenges in very large-scale SFQ scaling are also discussed.

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