Results with the TOFHIR2X Revision of the Front-end ASIC of the CMS MTD Barrel Timing Layer

Niknejad, T.; Albuquerque, E.; Benaglia, A.; Boletti, A.; Bugalho, R.; Guio, F. De; Firlej, M.; Fiutowski, T.; Francisco, R.; Gallinaro, M.; Ghezzi, A.; Idzik, Michał; Lucchini, M. T.; Malberti, M.; Moroń, J.; Oliveira, Luís B.; Pisano, M.; Redaelli, N.; Silva, J. C.; Silva, Rannyelly Eugênia Nascimento de Souza; Silveira, M.; Świentek, K.; Fatis, T. Tabarelli de; Varela, J.

doi:10.1109/nss/mic44867.2021.9875751

Cited by 5 publications

(5 citation statements)

References 2 publications

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“…Ultralow power and high sampling frequency, together with small pitch (and area), make the ADC a very attractive block for dedicated multi-channel readout systems in particle physics experiments. In fact, this ADC has been already implemented in the readout ASICs for the High Granularity Calorimeter [24] and for the MTD Barrel Timing layer [25] in the Upgraded CMS experiment at LHC.…”

Section: Discussionmentioning

confidence: 99%

An ultra-low power 10-bit, 50 MSps SAR ADC for multi-channel readout ASICs

Firlej,

Fiutowski,

Idzik

et al. 2023

J. Inst.

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The design and measurement results of a fast, ultra-low power, small area 10-bit SAR ADC, developed for multi-channel readout systems, in particular for applications in particle physics experiments, are discussed. A prototype ASIC was designed and fabricated in 130 nm CMOS technology and a wide spectrum of static (INL<0.4 LSB, DNL<0.3 LSB) and dynamic (ENOB=9.45) measurements was performed to study and quantify the performance of ADC. The ADC converts analogue signals with a sampling frequency up to 55 MHz and power consumption below 1 mW. The ADC works asynchronously, so no external clock is required. The ADC Figure of Merit (FOM) at 50 MHz sampling frequency is 24 fJ/conv.-step, and is the lowest among the State of the Art designs with similar technology and specifications.

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Section: Discussionmentioning

confidence: 99%

An ultra-low power 10-bit, 50 MSps SAR ADC for multi-channel readout ASICs

Firlej,

Fiutowski,

Idzik

et al. 2023

J. Inst.

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“…These performance levels must be achieved while respecting the specifications of power consumption mandated by cooling and power-delivery systems. These limits translate to a maximum power consumption (power budget) ranging from 0.1 W/ cm 2 [14] to 1.5 W/ cm 2 [12,15]. Furthermore, the ASIC architecture and technology must be sufficiently radiation-hard to sustain a total dose in the order of tens of megagrays [12].…”

Section: State Of the Art Of High Time Resolution Asicsmentioning

confidence: 99%

Timespot1: a 28 nm CMOS Pixel Read-Out ASIC for 4D Tracking at High Rates

et al. 2023

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We present the first characterization results of Timespot1, an ASIC designed in CMOS 28 nm technology, featuring a 32 × 32 pixel matrix with a pitch of 35 μm. Timespot1 is the first small-size prototype, conceived to readout fine-pitch pixels with single-hit time resolution below 50 psrms and input rates of several hundreds of kilohertz per pixel. Such experimental conditions will be typical of the next generation of high-luminosity collider experiments, from the LHC run5 and beyond. Each pixel of the ASIC includes a charge amplifier, a discriminator, and a Time-to-Digital Converter with a time resolution indicatively of 22.6 psrms and maximum readout rates (per pixel) of 3 MHz. To respect system-level constraints, the timing performance has been obtained keeping the power budget per pixel below 40 mW. The ASIC has been tested and characterised in the laboratory concerning its performance in terms of time resolution, power budget and sustainable rates. The ASIC will be hybridized on a matched 32 × 32 pixel sensor matrix and will be tested under laser beam and Minimum Ionizing Particles in the laboratory and at test beams. In this paper we present a description of the ASIC operation and the first results obtained from characterization tests concerning its performance.

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“…These performance levels must be achieved while respecting the specifications of power consumption posed by cooling and power-delivery systems. This limits translate to a maximum power consumption per unit area (power budget) ranging from 0.1 W/ cm 2 [10] to 1.5 W/ cm 2 [8] [11]. Furthermore, the ASIC architecture and technology must be sufficiently radiation-hard to sustain an total dose in the order of tens of megagrays [8].…”

Section: State Of the Art Of High Time Resolution Asicsmentioning

confidence: 99%

Timespot1: A 28nm CMOS Pixel Read-Out ASIC for 4D Tracking at High Rates

Cadeddu¹,

Frontini²,

Lai³

et al. 2022

Preprint

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A: We present the first characterization results of Timespot1, an ASIC designed in CMOS 28 nm technology, featuring a 32 × 32 pixel matrix with a pitch of 55 µm. Timespot1 is the first-born small-size prototype, conceived to read-out fine-pitch pixels with single-hit time resolution below 50 ps and input rates of several hundreds of kilohertz per pixel. Such experimental conditions will be typical of the next generation of high-luminosity collider experiments, from the LHC run5 and beyond. Each pixel of the ASIC has been endowed with a charge amplifier, a discriminator, and a Time-to-Digital Converter with time resolution around 30 ps and maximum read-out rates (per pixel) of 3 MHz. To respect system-level constraints, the timing performance have been obtained keeping the power budget per pixel below 40 µW. The ASIC has been tested and characterised in laboratory concerning its performance in terms of time resolution, power budget and sustainable rates. The ASIC will be hybridized on a matched 32 × 32 pixel sensor matrix and will be tested under laser beam and Minimum Ionizing Particles in the laboratory and at test beams. In this paper we present a description of the ASIC operation and the first results obtained from characterization tests concerning its performance in tracking measurements.

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Results with the TOFHIR2X Revision of the Front-end ASIC of the CMS MTD Barrel Timing Layer

Abstract: Results with the TOFHIR2X revision of the front-end ASIC of the CMS MTD Barrel Timing LayerTahereh Niknejad for the CMS MTD group

Cited by 5 publications

References 2 publications

An ultra-low power 10-bit, 50 MSps SAR ADC for multi-channel readout ASICs

An ultra-low power 10-bit, 50 MSps SAR ADC for multi-channel readout ASICs

Timespot1: a 28 nm CMOS Pixel Read-Out ASIC for 4D Tracking at High Rates

Timespot1: A 28nm CMOS Pixel Read-Out ASIC for 4D Tracking at High Rates

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