Rethinking algorithm-based fault tolerance with a cooperative software-hardware approach

Li, Dong; Chen, Zizhong; Wu, Panruo; Vetter, Jeffrey S.

doi:10.1145/2503210.2503226

Cited by 36 publications

(18 citation statements)

References 40 publications

(46 reference statements)

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“…We enrich the FRAM model with a safe memory of arbitrary size S and then give evidence that an increased safe memory can be exploited to notably improve the performance of resilient algorithms. In addition to its theoretical interest, the adoption of such a model is supported by recent research on hybrid systems that integrate algorithmic resiliency with the (limited) amount of memory protected by hardware ECC [17]. In this setting, S would denote the memory that is protected by the hardware.…”

Section: Our Resultsmentioning

confidence: 99%

Exploiting non-constant safe memory in resilient algorithms and data structures

Stefani

Silvestri

2015

Theoretical Computer Science

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We extend the Faulty RAM model by Finocchi and Italiano (2008) by adding a safe memory of arbitrary size S, and we then derive tradeoffs between the performance of resilient algorithmic techniques and the size of the safe memory. Let δ and α denote, respectively, the maximum amount of faults which can happen during the execution of an algorithm and the actual number of occurred faults, with α ≤ δ. We propose a resilient algorithm for sorting n entries which requires O (n log n + α(δ/S + log S)) time and uses Θ (S) safe memory words. Our algorithm outperforms previous resilient sorting algorithms which do not exploit the available safe memory and require O (n log n + αδ) time. Finally, we exploit our sorting algorithm for deriving a resilient priority queue. Our implementation uses Θ (S) safe memory words and Θ (n) faulty memory words for storing n keys, and requires O (log n + δ/S) amortized time for each insert and deletemin operation. Our resilient priority queue improves the O (log n + δ) amortized time required by the state of the art.

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Section: Our Resultsmentioning

confidence: 99%

Exploiting non-constant safe memory in resilient algorithms and data structures

Stefani

Silvestri

2015

Theoretical Computer Science

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“…With costs between 40%-85% vs 200%, our results may indicate an opportunity to disable ECC for DRAM and rather run ECC-unprotected when FlipSphere provides protection for kernels (not just for ECC-detectable events but also extra protection against silent data corruption), particularly since turning off ECC may result in lower memory latency and power consumption; yet, in contrast to Li at al. [23], FlipSphere does not require algorithmic changes.…”

Section: Discussionmentioning

confidence: 99%

FlipSphere: A Software-Based DRAM Error Detection and Correction Library for HPC

Fiala

Mueller

Ferreira

2016

2016 IEEE/ACM 20th International Symposium on Distributed Simulation and Real Time Applications (DS-RT)

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Proposed exascale systems will present considerable resiliency challenges. In particular, DRAM soft-errors, or bit-flips, are expected to greatly increase due to much higher memory density of these systems. Current hardware-based fault-tolerance methods cannot cope by itself with the expected soft error frequency rate. As a result, additional software is needed to address this challenge. We introduce FlipSphere, a tunable, transparent silent data corruption detection and correction library for HPC applications that is first in its class to use hardware accelerators such as the Intel Xeon Phi MIC to increase application resiliency. FlipSphere provides comprehensive silent data corruption protection for application memory by implementing on-demand page integrity verification coupled with software-based error correcting codes that allow for automatic error recovery in the event of memory failures. We investigate the trade-off of hardware resources for resilience and find that up to 90% of memory may be guarded with error detection at a 40% performance overhead.

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“…The design of solutions that combine capabilities across different layers of the system stack has also been previously explored, but using ad-hoc methods. For example, using the ABFT technique to protect application data structures permits different ECC mechanisms for different page frames in memory [13]. To deal with fail-stop and silent errors simultaneously, recent work has proposed combining ABFT methods with system-based checkpointing [2], in which each computational phase is followed by ABFT verification for SDCs and an in-memory checkpoint.…”

Section: Related Workmentioning

confidence: 99%

Pattern-based Modeling of Multiresilience Solutions for High-Performance Computing

Ashraf

Hukerikar

Engelmann

2018

Proceedings of the 2018 ACM/SPEC International Conference on Performance Engineering

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Resiliency is the ability of large-scale high-performance computing (HPC) applications to gracefully handle errors, and recover from failures. In this paper, we propose a pattern-based approach to constructing resilience solutions that handle multiple error modes. Using resilience patterns, we evaluate the performance and reliability characteristics of detection, containment and mitigation techniques for transient errors that cause silent data corruptions and techniques for fail-stop errors that result in process failures. We demonstrate the design and implementation of the multiresilience solution based on patterns instantiated across multiple layers of the system stack. The patterns are integrated to work together to achieve resiliency to different error types in a performance-efficient manner.

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Rethinking algorithm-based fault tolerance with a cooperative software-hardware approach

Cited by 36 publications

References 40 publications

Exploiting non-constant safe memory in resilient algorithms and data structures

Exploiting non-constant safe memory in resilient algorithms and data structures

FlipSphere: A Software-Based DRAM Error Detection and Correction Library for HPC

Pattern-based Modeling of Multiresilience Solutions for High-Performance Computing

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