Reticle Floorplanning and Simulated Wafer Dicing for Multiple-Project Wafers by Simulated Annealing

Lin, Rung-Bin; Wu, Meng-Chiou; Tsai, Shih-Cheng

doi:10.5772/5569

Cited by 1 publication

(4 citation statements)

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“…If δ=1, the objective function minimizes the reticle area; if δ=0, the objective function maximizes the compatibility. Irrespective of the forms of our function and Lin's function in (2), the main difference between these two functions is the normalizing factor. Lin use W max +H max in his normalizing factor, where W max and H max are the maximum allowable reticle width and height.…”

Section: Reticle Design For Wafer Dicingmentioning

confidence: 97%

“…However, the exact number of required wafer can only be obtained by simulation of wafer dicing, which is too time consuming for simulated annealing, since the number of required wafer needs to be calculated in every annealing procedure. We adopt an objective function which has the similar concept with the objective function based on VOCO in Lin's paper (2). It is based on the observation that two chips should be placed at the positions where no dicing conflict exists between them if their required production volumes are large to maximize the wafer utilization.…”

Section: Reticle Design For Wafer Dicingmentioning

confidence: 99%

“…We refer this concept as volume-defectdriven compatibility optimization or VDCO for short. The final cost function considering both wafer dicing and statistical model of defects becomes: [2] Where , , Y p and Y q are the defect limited yield for die p and q. If we substitute Y p and Y q with the formula in Poisson model, then , , W p , W q and H p , H q are width and height for chip p and q.…”

Section: Reticle Design Considering Both Wafer Dicing and Statistical...mentioning

confidence: 99%

“…The goal of reticle design is, given a reticle size, a set of dies with their sizes, required volume and the maximum margins, finding a die floorplan within the boundary of the reticle, and under certain wafer dicing plan, the required number of wafers is minimal. Recent works on reticle design have considered the yield loss caused by wafer dicing (2,3,4). They prefer a reticle design with less dicing conflicts, although the design may give out larger reticle size than the traditional design.…”

Section: Introductionmentioning

confidence: 99%

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Yield Enhanced Reticle Design Considering Both Wafer Dicing and Statistical Model of Defects

Zhu²,

Shi³

et al. 2012

ECS Trans.

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High mask cost increasingly motivates the use of Multiple Project Wafers (MPW). Prior to fabrication, dies chosen for an MPW program should be packed under certain constraints in a reticle, this is called reticle design. The goal of reticle design is using fewer wafers to get the required production volumes of all dies. In this paper, we proposed a yield enhanced reticle design algorithm which considers both wafer dicing and statistical model of defects. On the premise of ensuring required production volumes, the proposed algorithm gives improved average yield. During the reticle floorplan procedure, the die that needs larger production volume and has higher yield loss caused by random defect has higher penalty; therefore it will be placed at a proper position of the reticle automatically to avoid wafer dicing conflicts with the other dies. This approach results in better average yield which is in equivalence with fewer wafers.

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Section: Reticle Design For Wafer Dicingmentioning

confidence: 97%

Section: Reticle Design For Wafer Dicingmentioning

confidence: 99%

Section: Reticle Design Considering Both Wafer Dicing and Statistical...mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations