RETRACTED ARTICLE: Design of Software-based Global Navigation Satellite System Receiver for Satellite Applications

Abstract

Recent trends suggest Global Navigation Satellite System (GNSS) receiver technology has tremendous scope for satellite applications such as precise orbit determination and reflectometry. Space borne receivers are characterised by low-power requirements, high processing speed and radiation resistant electronic components. Such sophisticated receivers, also called hardware GNSS receivers, are fabricated for specific applications and hence lack of design flexibility. On the other hand, a software GNSS receiver allows easy design modifications without any hardware component replacement. Software receivers employ reconfigurable hardware elements called field-programmable gate arrays (FPGAs). Hardware designs can be implemented or modified in FPGAs using Hardware Description Language (HDL). In this research, a low-power, low-cost software GNSS receiver has been designed and developed using a combination of a microprocessor and FPGA, i.e. System on Chip (SoC). The developed software GNSS receiver is capable of detecting GPS satellites, tracking these signals and computing receiver position estimates. Efficient task partitioning is achieved by implementing operations in both the FPGA and the microprocessor. Also demonstrated in the improvement of processing speed by 20% when certain GNSS receiver operations are performed in the FPGA instead of the microprocessor.

SoC opportunities for boosting SDR GNSS performance

“…A typical SoC is a combination of FPGA and a hardware processor system (HPS), allowing parallel acquisition and/or tracking and sequential computation of coordinates. The analysis if recent publications [3][4][5][6][7] shows, that SoC is considered to be used for SDR-based GNSS receivers, however most of the authors use FPGA parts of their SoCs to synthesize additional cores rather than to design their own implementation of computational modules. Another problem is that SoC's FPGA part is not as large as of FPGA-only solutions.…”