Retrograde p-Well for 10-kV Class SiC IGBTs

Tiwari, Amit K.; Antoniou, Marina; Lophitis, Neophytos; Perkin, Samuel; Trajković, T.; Udrea, F.

doi:10.1109/ted.2019.2918008

Cited by 29 publications

(16 citation statements)

References 35 publications

(94 reference statements)

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“…2. The BV of the conventional SiC power MOSFET is 1368 V, and the proposed structure is 1556 V owing to a better depletion effect by the RP structure [5, 6 ]. The on‐state resistance of the conventional SiC power MOSFET and the proposed structure are 6.48 and 9.23 mΩ·cm 2 at a current density of 100 A/cm 2 , respectively.…”

Section: Resultsmentioning

confidence: 99%

Reliability enhanced SiC MOSFET with partially widened retrograde P‐well structure

et al. 2020

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In this Letter, a 1.2 kV SiC power MOSFET with a partially widened retrograde P-well (RP) structure and N-implanting region is proposed to enhance the device's reliability. Compared with the conventional SiC power MOSFET, the short circuit (SC) ability of the proposed structure can be improved effectively without sacrificing other performance. Simulation results reveal that a 40% reduction of the SC saturation current can be achieved, resulting in the SC withstand time increase from 7 to 10 μs at the DC-link voltage 800 V. Moreover, a better gate oxide reliability at 1.2 kV blocking condition also can be achieved. The peak electric field at the gate oxide interface is decreased by ∼48% owing to the shielding effect of the RP structure. In addition, the fabrication technology of the proposed structure is compatible with the standard planar SiC MOSFET manufacture process only with a few additional implanting steps. Therefore, this new MOSFET structure provides a simple and effective way to optimise the reliability of the planar SiC power MOSFET.

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Section: Resultsmentioning

confidence: 99%

Reliability enhanced SiC MOSFET with partially widened retrograde P‐well structure

et al. 2020

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“…1(b). The simulation uses previously calibrated models for critical semiconductor physics [9]- [11], including incomplete ionisation, impact ionisation, Shockley-Read-Hall (SRH) and Auger recombination, doping and temperature dependence and anisotropy of mobility, fixed charge and interface traps at the oxidesemiconductor interface. Additionally, nonisothermal equations are incorporated to account for the selfheating effects within the semiconductor.…”

Section: Device Structure Modeling and Simulationmentioning

confidence: 99%

Short-Circuit Performance Investigation of 10kV+ Rated SiC n-IGBT

Almpanis

Evans

Antoniou

et al. 2022

2022 IEEE Workshop on Wide Bandgap Power Devices and Applications in Europe (WiPDA Europe)

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This paper presents a comprehensive shortcircuit robustness investigation of 4H-Silicon Carbide (SiC) ntype Insulated Gate Bipolar Transistors (nIGBTs) for Medium-Voltage and High-Voltage applications. Numerical electrothermal TCAD simulations evaluate the IGBT shortcircuit behaviour under various conditions and device parameters variation. The internal device current density and temperature distribution show that the parasitic thyristor latchup and the thermally-assisted leakage current generation can be the failure mechanism of SiC nIGBT when the device temperature in the p-well/n-emitter interface region is about 1500K.

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“…For carrier mobility, the Masetti model describes the effect of doping and the Canali model describes the effect of temperature, the velocity saturation effect and interface degradation effect are also considered. The influence of temperature and doping on the energy bandgap and the incomplete ionization effect of dopants are also added [9].…”

Section: Device Description and Simulation Setupmentioning

confidence: 99%

Study and Optimization of Field Limiting Rings for 10kV SiC Insulated Gate Bipolar Transistor

Zhang

Wang

2021

Preprint

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A 10kV-level silicon carbide (SiC) insulated gate bipolar transistor (IGBT) with field limiting rings (FLRs) is designed and simulated with Sentaurus TCAD, the detailed optimization method and comparisons are presented in this paper. Linearly varying spacing between rings is introduced to SiC IGBT and adjustment is performed on width of rings, the final structure achieves a breakdown voltage over 12kV with a termination length of 164.5 µm , which is 69.93% lower than that of conventional structure with a fixed ring spacing. Moreover, the final design can decrease the sensitivity to the interface charges, the tolerance to positive surface charges exceeds 8 × 10 11 cm − 2 , which is 3.5 times that of the conventional structure. Besides, double pulse measurements prove no degradation of conduction and switching characteristics.

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Retrograde p-Well for 10-kV Class SiC IGBTs

Cited by 29 publications

References 35 publications

Reliability enhanced SiC MOSFET with partially widened retrograde P‐well structure

Reliability enhanced SiC MOSFET with partially widened retrograde P‐well structure

Short-Circuit Performance Investigation of 10kV+ Rated SiC n-IGBT

Study and Optimization of Field Limiting Rings for 10kV SiC Insulated Gate Bipolar Transistor

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