Retrospective: improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers

Cache-Content-Duplication (CCD) occurs when there is a miss for a block in a cache and the entire content of the missed block is already in the cache in a block with a different tag. Caches aware of content-duplication can have lower miss rates by allowing only blocks with unique content to enter a cache. This work examines the potential of CCD for instruction caches. We show that CCD is a frequent phenomenon and that an idealized duplicationdetection mechanism for instruction caches has the potential to increase performance of an out-of-order processor, with a 2-way eight instruction per block 16KB instruction cache, often by more than 5% and up to 20%. This work also proposes CATCH, a hardware based mechanism for dynamically detecting CCD. Experimental results for an out-of-order processor show that a CATCH with a 2.32KB cost usually captures 60% or more of the CCD's idealized potential. 109 103 148 115 Tag Content 109 r1=0+1, r2=r2+r3, if(r2)targ1 103 r3=82(r5), r4=0+r1, r3=r4+4 148 r6=0+r1, r1=r4+r2, if(!r1)targ2 115 r3=82(r5), r4=0+r1, r3=r4+4

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Retrospective: improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers

Cited by 8 publications

References 7 publications

Memory management optimization problems for integrated circuit simulators

Memory management optimization problems for integrated circuit simulators

Design and Verification of Cache Memory Decoder for High Speed Multicore Processor

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