Revealing the Mechanism of the Bias Temperature Instability Effect of p-GaN Gate HEMTs by Time-Dependent Gate Breakdown Stress and Fast Sweeping Characterization

Li, Xiangdong; Wang, Meng; Zhang, Jincheng; Gao, Rui; Wang, Hongyue; Yang, Weitao; Yuan, Jiahui; You, Shuzhen; Chang, Jingjing; Liu, Zhihong; Hao, Yue

doi:10.3390/mi14051042

Cited by 6 publications

(2 citation statements)

References 27 publications

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“…NBT stress-induced threshold voltage shifts have been found in n-type trench DMOS transistors [30]. Previous research of NBTI in power VDMOSFETs led to a rather similar finding [31,32].…”

Section: Oxide Trapped Charge and Interface Trapssupporting

confidence: 52%

“…However, having in mind that high negative gate bias can be used in some automotive applications for the faster turning off of the NMOS devices, rather significant NBT stress-induced threshold voltage shifts have been found in n-type trench DMOS transistors [30]. Previous research of NBTI in power VDMOSFETs led to a rather similar finding [31,32]. The dependencies of the underlying buildup of gate oxide trapped charge and interface traps on stress time under stress bias (at 150 • C) and temperature (at −/+40 V) are illustrated in Figures 6-8.…”

Section: Oxide Trapped Charge and Interface Trapsmentioning

confidence: 83%

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A Reliability Investigation of VDMOS Transistors: Performance and Degradation Caused by Bias Temperature Stress

Živanović,

Veljković,

Mitrović

et al. 2024

Micromachines

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This study aimed to comprehensively understand the performance and degradation of both p- and n-channel vertical double diffused MOS (VDMOS) transistors under bias temperature stress. Conducted experimental investigations involved various stress conditions and annealing processes to analyze the impacts of BT stress on the formation of oxide trapped charge and interface traps, leading to threshold voltage shifts. Findings revealed meaningful threshold voltage shifts in both PMOS and NMOS devices due to stresses, and the subsequent annealing process was analyzed in detail. The study also examined the influence of stress history on self-heating behavior under real operating conditions. Additionally, the study elucidated the complex correlation between stress-induced degradation and device reliability. The insights contribute to optimizing the performance and permanence of VDMOS transistors in practical applications, advancing semiconductor technology. This study underscored the importance of considering stress-induced effects on device reliability and performance in the design and application of VDMOS transistors.

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“…NBT stress-induced threshold voltage shifts have been found in n-type trench DMOS transistors [30]. Previous research of NBTI in power VDMOSFETs led to a rather similar finding [31,32].…”

Section: Oxide Trapped Charge and Interface Trapssupporting

confidence: 52%

Section: Oxide Trapped Charge and Interface Trapsmentioning

confidence: 83%

A Reliability Investigation of VDMOS Transistors: Performance and Degradation Caused by Bias Temperature Stress

Živanović,

Veljković,

Mitrović

et al. 2024

Micromachines

View full text Add to dashboard Cite

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Physical Modeling of Threshold Voltage Instability in GaN High‐Electron‐Mobility Transistors

Mao

2024

Physica Status Solidi (a)

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The transient heat conduction equation for the 2D electron gas layer in GaN high‐electron‐mobility transistors is developed. The Schottky barrier height and the conduction band offset seen by electrons in the 2D electron gas layer will be reduced due to self‐heating in the 2D electron gas of GaN high‐electron‐mobility transistors via quantum coupling. Such a reduction will lead to a shift in the threshold voltage. To address this issue, an analytical physical model of self‐heating in the 2D electron gas of a GaN high‐electron‐mobility transistor via quantum coupling impacts on its threshold voltage instability is proposed. The proposed model forecasts that the threshold voltage can have an exponentially dependent relation with the reciprocal of the recovery time after the stress voltage is released, as well as dependencies on the square of the drift velocity, the gate voltage, and the surrounding temperature. The experimentally observed threshold voltage shifts of GaN high‐electron‐mobility transistors confirm such dependent relationships predicted by the proposed physical model. This article provides evidence that the combination of self‐heating in the 2D electron gas layer and quantum coupling may be a possible physical origin of the threshold voltage instability in GaN high‐electron‐mobility transistors.

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Quantum coupling and self-heating impacts on threshold voltages of GaN metal–insulator-semiconductor high-electron-mobility transistors

Mao

2024

Results in Physics

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Revealing the Mechanism of the Bias Temperature Instability Effect of p-GaN Gate HEMTs by Time-Dependent Gate Breakdown Stress and Fast Sweeping Characterization

Cited by 6 publications

References 27 publications

A Reliability Investigation of VDMOS Transistors: Performance and Degradation Caused by Bias Temperature Stress

A Reliability Investigation of VDMOS Transistors: Performance and Degradation Caused by Bias Temperature Stress

Physical Modeling of Threshold Voltage Instability in GaN High‐Electron‐Mobility Transistors

Quantum coupling and self-heating impacts on threshold voltages of GaN metal–insulator-semiconductor high-electron-mobility transistors

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