Review of Elliptic Curve Cryptography processor designs

Marzouqi, Hamad; Al‐Qutayri, Mahmoud; Salah, Khaled

doi:10.1016/j.micpro.2015.02.003

Cited by 41 publications

(21 citation statements)

References 68 publications

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“…To avoid being exhaustive on the topic, we focus on more recent hardware implementations of ECC over prime fields. For those interested more generally in the topic, a recent survey is done by Marzouqi et al [15].…”

Section: Ecc Hardware Implementationsmentioning

confidence: 99%

Completing the Complete ECC Formulae with Countermeasures

Chmielewski¹,

Massolino

Vliegen

et al. 2017

JLPEA

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This work implements and evaluates the recent complete addition formulae for the prime order elliptic curves of Renes, Costello and Batina on an FPGA platform. We implement three different versions: (1) an unprotected architecture; (2) an architecture protected through coordinate randomization; and (3) an architecture with both coordinate randomization and scalar splitting in place. The evaluation is done through timing analysis and test vector leakage assessment (TVLA). The results show that applying an increasing level of countermeasures leads to an increasing resistance against side-channel attacks. This is the first work looking into side-channel security issues of hardware implementations of the complete formulae.

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Section: Ecc Hardware Implementationsmentioning

confidence: 99%

Completing the Complete ECC Formulae with Countermeasures

Chmielewski¹,

Massolino

Vliegen

et al. 2017

JLPEA

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“…Anywhere, anytime and with anything it can be connected. To any range of traditionally dumb or non-internet-enabled physical devices and everyday objects are included by extending internet connectivity beyond standard devices like desktops, laptops, smart phones and tablets [2]. Over the internet these devices can communicate and interact also they can be remotely monitored and controlled embedded with the technology.…”

Section: Introductionmentioning

confidence: 99%

Threshold-Based Method for Detection of Distributed Denial of Service Attack in IoT

Joseph*,

Dutta

2019

IJRTE

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The internet of things is the decentralized type of network in which sensor devices can join or leave the network when they want. Due to such nature of the network malicious nodes enter the network which affects network performance in terms of certain parameters. This research work is based on the detection and isolation of distributed denial of service attack in internet of things. The distributed denial of service attack is the denial of service type attack which affects network performance to large extent. In the existing techniques there are two main drawbacks. The first drawback is that the technique does not pin point malicious nodes from the network. The second drawback is that the malicious node detection time is very high. In this research, the new technique will be proposed for the isolation of malicious nodes from the network. In this technique, similarity of the traffic is analyzed using the cosine similarity. The sensor node which is generated dissimilar type of traffic is detected as malicious nodes. The proposed technique has been implemented in MATLAB and results have been analyzed in terms of certain parameters. It is expected that proposed technique detect malicious nodes in least amount of time.

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“…Many hardware implementations of ECC have been proposed [6][7][8][9][10][11][12][13][14][15][16][17][18] for ECC. The accelerator of modular multiplication (MM) can be divided into two categories: multiplier-based architecture and adder-based architectures.…”

Section: Introductionmentioning

confidence: 99%

A Low Hardware Consumption Elliptic Curve Cryptographic Architecture over GF(p) in Embedded Application

Zheng

Zhang

et al. 2018

Electronics

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Abstract:In this paper, a low hardware consumption design of elliptic curve cryptography (ECC) over GF(p) in embedded applications is proposed. The adder-based architecture is explored to reduce the hardware consumption of performing scalar multiplication (SM). The Interleaved Modular Multiplication Algorithm and Binary Modular Inversion Algorithm are improved and implemented with two full-word adder units. The full-word register units for data storage are also optimized. The design is based on two full-word adder units and twelve full-word register units of pipeline structure and was implemented on Xilinx Virtex-4 platform. Design Compiler is used to synthesized the proposed architecture with 0.13 µm CMOS standard cell library. For 160, 192, 224, 256 field order, the proposed architecture consumes 5595, 7080, 8423, 9370 slices, respectively, and saves 17.58∼54.93% slice resources on FPGA platform when compared with other design architectures. The synthesized result uses 35.43 k, 43.37 k, 50.38 k, 57.05 k gate area and saves 52.56∼91.34% in terms of gate count in comparison. The design takes 2.56∼4.07 ms to perform SM operation over different field order under 150 MHz frequency. The proposed architecture is safe from simple power analysis (SPA). Thus, it is a good choice for embedded applications.

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Review of Elliptic Curve Cryptography processor designs

Cited by 41 publications

References 68 publications

Completing the Complete ECC Formulae with Countermeasures

Completing the Complete ECC Formulae with Countermeasures

Threshold-Based Method for Detection of Distributed Denial of Service Attack in IoT

A Low Hardware Consumption Elliptic Curve Cryptographic Architecture over GF(p) in Embedded Application

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