Review of profile and roughening simulation in microelectronics plasma etching

Abstract

Plasma etching of thin films is essential for microelectronics manufacturing. With current feature sizes of 35 nm in production and processes for smaller devices being developed, the sidewall roughness is within the order of magnitude of the gate length of the device, and therefore significantly impacts the devices' performance. In this paper we review the modelling of the surface profile evolution in plasma etching. Both two-dimensional (2D) and three-dimensional (3D) models have been developed using a number of representations and solution algorithms. String algorithms and the method of characteristics use a segmented string which is incrementally advanced. Level-set representations describe the profile evolution as a moving interface in response to a velocity field. Cellular representations in which the area or volume domain is divided into discrete cells have been used with flux and surface kinetics based on Monte Carlo calculations. We discuss our work in the modelling of profile evolution with surface roughening using a 3D cellular Monte Carlo simulation. The formation of perpendicular and parallel ripple formation on planar surfaces as a function of ion bombardment incidence angle and the transformation from perpendicular to parallel as etching progresses has been modelled. The smoothing and/or roughening of resist masks has been demonstrated along with the pattern transfer of roughness into the underlying layers being etched.

An atomic force microscopy-based method for line edge roughness measurement

“…They both show an anisotropic morphology of the sidewall roughness after the lithography step which is accentuated during the subsequent plasma etching steps because of the directionality of the ion flux. 16 This observation is in full agreement with a previous study. 17 However, while X-SEM gives good qualitative analyses of roughness, the developed AFM technique can also be used to obtain a quantitative estimation of the roughness and to calculate the LER all along the pattern height after each plasma etching step involved in the patterning as shown in Figure 6(b).…”

Modeling of Charging on Unconventional Surface Morphologies of PMMA Substrates During Ar Plasma Etching

“…Surface roughness of polymeric substrates is important not only in micro-and nanoelectronics {e.g., line edge roughness (LER) issue [1][2][3] }, but also for several applications in other fields. For example, it affects wetting and optical properties of surfaces, [4,5] the adsorption of proteins on surfaces, [6,7] and the cell adhesion and growth.…”

Towards control of plasma-induced surface roughness: simultaneous to plasma etching deposition

“…a model which includes the effect of impurities or etch-inhibitors or depositing particles for the explanation of pattern formation during IBS of Si was pinpointed by Macko et al in a recent work [14]. There are interesting modeling works with focus on surface roughness and pattern formation which refer either to etching only [22][23][24][25] or deposition only [26,27]. A first effort to model SIMED with a (1+1)d stochastic modeling framework was reported in [28], where it was shown that SIMED could lead to an instability in roughness evolution versus time (linear increase of root mean square of roughness versus time) and dual scale surface roughness.…”