2013 15th European Conference on Power Electronics and Applications (EPE) 2013
DOI: 10.1109/epe.2013.6632001
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Review of state-of-the-art solver solutions for HIL simulation of power systems, power electronic and motor drives

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Cited by 27 publications
(7 citation statements)
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“…There is no communication link between VSCs, the controller for the real inverter is implemented in MATLAB/Simulink and compiled for DS1005 dSpace target hardware. The RT VSCs controllers are implemented in MATLAB/Simulink as well, and the corresponding compilation is sent via TCP/IP to the RT-LAB platform [30]- [32]. In this test, the output currents magnitudes are fixed to 7A peak to easily show the performance of the proposed technique.…”
Section: Resultsmentioning
confidence: 99%
“…There is no communication link between VSCs, the controller for the real inverter is implemented in MATLAB/Simulink and compiled for DS1005 dSpace target hardware. The RT VSCs controllers are implemented in MATLAB/Simulink as well, and the corresponding compilation is sent via TCP/IP to the RT-LAB platform [30]- [32]. In this test, the output currents magnitudes are fixed to 7A peak to easily show the performance of the proposed technique.…”
Section: Resultsmentioning
confidence: 99%
“…Importantly, some simulators can be expanded by communicating two or more units. One can also consider hardware technology as a benchmark (Dufour et al 2013): some simulators use multi-core CPUs and other FPGAs. Real-time simulators for power systems are commonly compared in terms of AC nodes, considering that these nodes will be resolved within a sufficient time frame (usually 50 µs).…”
Section: Typhoonmentioning
confidence: 99%
“…FPGA is considered as the best candidate for implementing RTDS, due to its parallel processing hardware structure, which allows implementing different algorithms with reducing the sequencing of operation comparing with CPUs implementation. In addition, FPGA-RTDS offers more specifications, which required for accurate real time simulation, such as lower I/O latency, higher frequency bandwidth and lower sampling rate below 1 µs typically [25,26]. Reference [24] utilized an FPGA-RTDS as a part of smart replacement real-time hardware-in-the-loop simulation platform.…”
Section: Hardware Implementation Based On Fpgamentioning
confidence: 99%